951 #define MLX5_CAP_GEN(mdev, cap) \  argument
952 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
954 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
955 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
957 #define MLX5_CAP_ETH(mdev, cap) \  argument
959 		 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
961 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
963 		 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
965 #define MLX5_CAP_ROCE(mdev, cap) \  argument
966 	MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
968 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
969 	MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
971 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
972 	MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
974 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
975 	MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
977 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
978 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
980 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
981 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
983 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
985 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
987 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
989 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
991 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
992 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
994 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
995 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
997 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
998 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1000 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1001 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1003 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1004 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1006 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1007 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1009 #define MLX5_CAP_ESW(mdev, cap) \  argument
1011 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1013 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1015 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1017 #define MLX5_CAP_ODP(mdev, cap)\  argument
1018 	MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1020 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1021 	MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1023 #define MLX5_CAP_SNAPSHOT(mdev, cap) \  argument
1025 		 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1027 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \  argument
1029 		 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1031 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \  argument
1033 		 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1035 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \  argument
1037 		 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1039 #define MLX5_CAP_DEBUG(mdev, cap) \  argument
1041 		 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1043 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \  argument
1045 		 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1047 #define MLX5_CAP_QOS(mdev, cap) \  argument
1049 		 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1051 #define MLX5_CAP_QOS_MAX(mdev, cap) \  argument
1053 		 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1055 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \  argument
1056 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1058 #define	MLX5_CAP_PCAM_REG(mdev, reg) \  argument
1059 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1061 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \  argument
1062 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1064 #define	MLX5_CAP_MCAM_REG(mdev, reg) \  argument
1065 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1067 #define	MLX5_CAP_QCAM_REG(mdev, fld) \  argument
1068 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1070 #define	MLX5_CAP_QCAM_FEATURE(mdev, fld) \  argument
1071 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1073 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1074 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1076 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1077 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)