145 	CSR_WRITE_2(sc, EP_W0_EEPROM_COMMAND,  in ep_get_e()
409 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);  in epinit_locked()
411 	CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);  in epinit_locked()
415 	CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, 0);  in epinit_locked()
418 	CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);  in epinit_locked()
424 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);  in epinit_locked()
425 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);  in epinit_locked()
434 	CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);  in epinit_locked()
436 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);  in epinit_locked()
437 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);  in epinit_locked()
440 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |  in epinit_locked()
443 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |  in epinit_locked()
450 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);  in epinit_locked()
451 	CSR_WRITE_2(sc, EP_COMMAND, RX_ENABLE);  in epinit_locked()
452 	CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);  in epinit_locked()
466 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);  in epinit_locked()
467 	CSR_WRITE_2(sc, EP_COMMAND, SET_TX_START_THRESH | 16);  in epinit_locked()
506 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);  in epstart_locked()
526 		CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));  in epstart_locked()
534 		CSR_WRITE_2(sc, EP_COMMAND,  in epstart_locked()
537 	CSR_WRITE_2(sc, EP_W1_TX_PIO_WR_1, len);  in epstart_locked()
539 	CSR_WRITE_2(sc, EP_W1_TX_PIO_WR_1, 0x0);  in epstart_locked()
572 			CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | 8);  in epstart_locked()
606 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);	/* disable all Ints */  in ep_intr_locked()
613 		CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | (status & S_MASK));  in ep_intr_locked()
667 					CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);  in ep_intr_locked()
681 					CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);  in ep_intr_locked()
687 						CSR_WRITE_2(sc, EP_COMMAND,  in ep_intr_locked()
700 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);	/* ACK int Latch */  in ep_intr_locked()
706 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);  in ep_intr_locked()
807 		CSR_WRITE_2(sc, EP_COMMAND,  in epread()
811 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);  in epread()
829 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);  in epread()
833 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);  in epread()
843 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);  in epread()
853 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);  in ep_ifmedia_upd()
855 	CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);  in ep_ifmedia_upd()
863 			CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, ENABLE_UTP);  in ep_ifmedia_upd()
869 			CSR_WRITE_2(sc, EP_COMMAND, START_TRANSCEIVER);  in ep_ifmedia_upd()
885 	CSR_WRITE_2(sc, EP_W0_ADDRESS_CFG, j | (i << ACF_CONNECTOR_BITS));  in ep_ifmedia_upd()
988 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISABLE);  in epstop()
989 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);  in epstop()
992 	CSR_WRITE_2(sc, EP_COMMAND, TX_DISABLE);  in epstop()
993 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);  in epstop()
996 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);  in epstop()
998 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);  in epstop()
1001 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);  in epstop()
1002 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK);  in epstop()
1003 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);  in epstop()
1004 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER);  in epstop()