Lines Matching refs:upper_32_bits
1818 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()
1850 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); in si_ring_ib_execute()
1863 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in si_ring_ib_execute()
2070 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
2103 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
2129 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3003 radeon_ring_write(ring, upper_32_bits(pe)); in si_vm_set_page()
3016 radeon_ring_write(ring, upper_32_bits(value)); in si_vm_set_page()
3030 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); in si_vm_set_page()
3043 radeon_ring_write(ring, upper_32_bits(value)); in si_vm_set_page()
3059 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); in si_vm_set_page()
3063 radeon_ring_write(ring, upper_32_bits(value)); in si_vm_set_page()
3400 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in si_irq_init()
4090 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
4091 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()