Lines Matching refs:INT_MASK
3316 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
3317 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
3319 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
3320 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
3323 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
3324 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
3544 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in si_irq_set()
3545 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in si_irq_set()
3547 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in si_irq_set()
3548 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in si_irq_set()
3551 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in si_irq_set()
3552 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in si_irq_set()