Lines Matching +full:sumo2_me +full:. +full:bin
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
14 * all copies or substantial portions of the Software.
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * OTHER DEALINGS IN THE SOFTWARE.
29 #include <sys/cdefs.h>
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/radeon/radeon_drm.h>
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
37 #include "r600d.h"
38 #include "atom.h"
39 #include "avivod.h"
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
101 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
105 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
128 rdev->pm.dynpm_can_upclock = true; in r600_pm_get_dynpm_state()
129 rdev->pm.dynpm_can_downclock = true; in r600_pm_get_dynpm_state()
135 if (rdev->pm.num_power_states > 2) in r600_pm_get_dynpm_state()
138 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
140 rdev->pm.requested_power_state_index = min_power_state_index; in r600_pm_get_dynpm_state()
141 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
142 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
145 if (rdev->pm.current_power_state_index == min_power_state_index) { in r600_pm_get_dynpm_state()
146 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
147 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
149 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
150 for (i = 0; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
151 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
153 else if (i >= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
154 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
155 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
158 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
163 if (rdev->pm.current_power_state_index == 0) in r600_pm_get_dynpm_state()
164 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
165 rdev->pm.num_power_states - 1; in r600_pm_get_dynpm_state()
167 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
168 rdev->pm.current_power_state_index - 1; in r600_pm_get_dynpm_state()
171 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
173 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
174 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
175 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
177 rdev->pm.requested_power_state_index++; in r600_pm_get_dynpm_state()
181 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r600_pm_get_dynpm_state()
182 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
183 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
185 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
186 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r600_pm_get_dynpm_state()
187 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
189 else if (i <= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
190 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
191 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
194 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
199 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
200 rdev->pm.current_power_state_index + 1; in r600_pm_get_dynpm_state()
202 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
205 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
206 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
207 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
215 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ in r600_pm_get_dynpm_state()
218 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
219 rdev->pm.requested_power_state_index = -1; in r600_pm_get_dynpm_state()
221 for (i = 1; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
222 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
224 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || in r600_pm_get_dynpm_state()
225 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { in r600_pm_get_dynpm_state()
226 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
230 /* if nothing selected, grab the default state. */ in r600_pm_get_dynpm_state()
231 if (rdev->pm.requested_power_state_index == -1) in r600_pm_get_dynpm_state()
232 rdev->pm.requested_power_state_index = 0; in r600_pm_get_dynpm_state()
234 rdev->pm.requested_power_state_index = 1; in r600_pm_get_dynpm_state()
236 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
238 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
239 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
242 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
243 if (rdev->pm.current_clock_mode_index == 0) { in r600_pm_get_dynpm_state()
244 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
245 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
247 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
248 rdev->pm.current_clock_mode_index - 1; in r600_pm_get_dynpm_state()
250 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
251 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
254 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
255 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
256 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
258 rdev->pm.requested_clock_mode_index++; in r600_pm_get_dynpm_state()
262 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
263 if (rdev->pm.current_clock_mode_index == in r600_pm_get_dynpm_state()
264 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { in r600_pm_get_dynpm_state()
265 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; in r600_pm_get_dynpm_state()
266 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
268 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
269 rdev->pm.current_clock_mode_index + 1; in r600_pm_get_dynpm_state()
271 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
272 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; in r600_pm_get_dynpm_state()
273 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
277 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
278 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
279 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
289 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
290 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r600_pm_get_dynpm_state()
291 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
292 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r600_pm_get_dynpm_state()
293 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
299 if (rdev->pm.num_power_states == 2) { in rs780_pm_init_profile()
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
335 } else if (rdev->pm.num_power_states == 3) { in rs780_pm_init_profile()
337 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
339 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
340 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
342 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
344 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
345 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
349 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
350 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
352 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
354 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
355 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
357 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
359 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
360 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
362 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
364 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
365 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
369 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
370 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
373 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
374 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
375 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
376 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
378 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
379 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
380 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
381 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
383 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
384 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
385 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
386 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
388 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
389 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
390 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
391 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
393 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
394 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
395 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
396 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
398 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
399 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
400 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
401 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
403 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
404 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
405 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
406 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
417 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
418 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
419 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
420 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
422 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
423 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
424 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
425 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
427 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
428 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
429 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
430 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
432 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
433 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
434 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
435 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
437 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
438 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
439 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
440 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
442 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
443 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
444 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
445 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
447 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
448 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
449 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
450 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
452 if (rdev->pm.num_power_states < 4) { in r600_pm_init_profile()
454 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
455 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
456 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
459 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
460 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
461 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
462 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
464 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
465 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
466 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
467 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
469 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
470 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
471 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
472 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
474 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
475 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
476 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
477 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
479 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
480 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
481 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
484 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
485 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
486 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
487 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
490 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
491 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
492 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
493 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
499 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
500 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
501 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
502 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
504 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
505 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
506 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
507 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
510 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
511 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
512 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
513 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
519 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
520 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
521 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
522 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
524 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
525 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
526 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
527 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
530 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
531 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
532 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
533 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
540 int req_ps_idx = rdev->pm.requested_power_state_index; in r600_pm_misc()
541 int req_cm_idx = rdev->pm.requested_clock_mode_index; in r600_pm_misc()
542 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in r600_pm_misc()
543 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; in r600_pm_misc()
549 if (voltage->voltage != rdev->pm.current_vddc) { in r600_pm_misc()
551 rdev->pm.current_vddc = voltage->voltage; in r600_pm_misc()
719 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r600_hpd_init()
726 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 in r600_hpd_init()
735 switch (radeon_connector->hpd.hpd) { in r600_hpd_init()
759 switch (radeon_connector->hpd.hpd) { in r600_hpd_init()
773 enable |= 1 << radeon_connector->hpd.hpd; in r600_hpd_init()
774 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r600_hpd_init()
785 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r600_hpd_fini()
788 switch (radeon_connector->hpd.hpd) { in r600_hpd_fini()
812 switch (radeon_connector->hpd.hpd) { in r600_hpd_fini()
826 disable |= 1 << radeon_connector->hpd.hpd; in r600_hpd_fini()
842 volatile uint32_t *ptr = rdev->gart.ptr; in r600_pcie_gart_tlb_flush()
845 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read in r600_pcie_gart_tlb_flush()
847 * This seems to cause problems on some AGP cards. Just use the old in r600_pcie_gart_tlb_flush()
848 * method for them. in r600_pcie_gart_tlb_flush()
855 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
856 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
877 if (rdev->gart.robj) { in r600_pcie_gart_init()
885 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in r600_pcie_gart_init()
894 if (rdev->gart.robj == NULL) { in r600_pcie_gart_enable()
895 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in r600_pcie_gart_enable()
928 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
929 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
930 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
934 (u32)(rdev->dummy_page.addr >> 12)); in r600_pcie_gart_enable()
939 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in r600_pcie_gart_enable()
940 (unsigned)(rdev->mc.gtt_size >> 20), in r600_pcie_gart_enable()
941 (unsigned long long)rdev->gart.table_addr); in r600_pcie_gart_enable()
942 rdev->gart.ready = true; in r600_pcie_gart_enable()
1059 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1062 rdev->mc.vram_start >> 12); in r600_mc_program()
1064 rdev->mc.gtt_end >> 12); in r600_mc_program()
1068 rdev->mc.gtt_start >> 12); in r600_mc_program()
1070 rdev->mc.vram_end >> 12); in r600_mc_program()
1073 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1074 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1076 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1077 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1078 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1080 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1084 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1085 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1086 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1108 * different address space.
1111 * aperture then we limit the VRAM size to the aperture.
1115 * catch access outside them (weird GPU policy see ??).
1117 * This function will never fails, worst case are limiting VRAM or GTT.
1120 * function on AGP platform.
1161 rdev->mc.gtt_base_align = 0; in r600_vram_gtt_location()
1172 rdev->mc.vram_is_ddr = true; in r600_mc_init()
1197 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
1199 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); in r600_mc_init()
1200 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); in r600_mc_init()
1202 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1203 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1204 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1209 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in r600_mc_init()
1218 void *vram_scratch_ptr_ptr; /* FreeBSD: to please GCC 4.2. */ in r600_vram_scratch_init()
1220 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_init()
1223 NULL, &rdev->vram_scratch.robj); in r600_vram_scratch_init()
1229 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_init()
1231 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_init()
1234 r = radeon_bo_pin(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1235 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); in r600_vram_scratch_init()
1237 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1238 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_init()
1241 vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr; in r600_vram_scratch_init()
1242 r = radeon_bo_kmap(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1245 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1246 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1248 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_init()
1257 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_fini()
1260 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_fini()
1262 radeon_bo_kunmap(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1263 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1264 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1266 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1270 * reset, it's up to the caller to determine if the GPU needs one. We
1271 * might add an helper function to check that.
1446 * Check if the async DMA engine is locked up (r6xx-evergreen).
1447 * Returns true if the engine appears to be locked up, false if not.
1541 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
1544 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1545 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
1546 rdev->config.r600.max_simds = 4; in r600_gpu_init()
1547 rdev->config.r600.max_backends = 4; in r600_gpu_init()
1548 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
1549 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1550 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
1551 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1552 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
1553 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1554 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1555 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1556 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1560 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
1561 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
1562 rdev->config.r600.max_simds = 3; in r600_gpu_init()
1563 rdev->config.r600.max_backends = 1; in r600_gpu_init()
1564 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
1565 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1566 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
1567 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1568 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
1569 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1570 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1571 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1572 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1578 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
1579 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
1580 rdev->config.r600.max_simds = 2; in r600_gpu_init()
1581 rdev->config.r600.max_backends = 1; in r600_gpu_init()
1582 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
1583 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1584 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
1585 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
1586 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
1587 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1588 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1589 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1590 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
1593 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1594 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
1595 rdev->config.r600.max_simds = 4; in r600_gpu_init()
1596 rdev->config.r600.max_backends = 4; in r600_gpu_init()
1597 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
1598 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1599 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
1600 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1601 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
1602 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1603 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1604 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1605 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1625 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
1641 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
1642 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
1659 if (tmp < rdev->config.r600.max_backends) { in r600_gpu_init()
1660 rdev->config.r600.max_backends = tmp; in r600_gpu_init()
1666 if (tmp < rdev->config.r600.max_pipes) { in r600_gpu_init()
1667 rdev->config.r600.max_pipes = tmp; in r600_gpu_init()
1671 if (tmp < rdev->config.r600.max_simds) { in r600_gpu_init()
1672 rdev->config.r600.max_simds = tmp; in r600_gpu_init()
1677 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
1680 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
1682 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
1744 * should be adjusted as needed by the 2D/3D drivers. This just sets default values in r600_gpu_init()
1839 /* More default values. 2D/3D driver should adjust as needed */ in r600_gpu_init()
1856 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
1878 /* more default values. 2D/3D driver should adjust as needed */ in r600_gpu_init()
1961 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_cp_stop()
1964 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_cp_stop()
2136 * Drop the pfp, me and rlc firmwares image references.
2137 * Called at driver shutdown.
2208 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); in r600_cp_start()
2215 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2218 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2263 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2264 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2265 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2267 if (rdev->wb.enabled) in r600_cp_resume()
2306 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); in r600_ring_init()
2323 * DMA engine. The programming model is very similar
2324 * to the 3D engine (ring buffer, IBs, etc.), but the
2326 * different form the PM4 format used by the 3D engine.
2328 * solid fills, and a number of other things. It also
2329 * has support for tiling/detiling of buffers.
2336 * Stop the async dma engine (r6xx-evergreen).
2342 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_dma_stop()
2347 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; in r600_dma_stop()
2355 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2356 * Returns 0 for success, error for failure.
2391 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
2393 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_dma_resume()
2395 if (rdev->wb.enabled) in r600_dma_resume()
2429 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r600_dma_resume()
2439 * Stop the async dma engine and free the ring (r6xx-evergreen).
2448 * GPU scratch registers helpers function.
2454 rdev->scratch.num_reg = 7; in r600_scratch_init()
2455 rdev->scratch.reg_base = SCRATCH_REG0; in r600_scratch_init()
2456 for (i = 0; i < rdev->scratch.num_reg; i++) { in r600_scratch_init()
2457 rdev->scratch.free[i] = true; in r600_scratch_init()
2458 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in r600_scratch_init()
2471 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); in r600_ring_test()
2477 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); in r600_ring_test()
2509 * value to memory. (r6xx-SI).
2510 * Returns 0 for success, error for failure.
2517 volatile uint32_t *ptr = rdev->vram_scratch.ptr; in r600_dma_ring_test()
2530 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); in r600_dma_ring_test()
2534 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); in r600_dma_ring_test()
2535 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); in r600_dma_ring_test()
2565 if (rdev->wb.use_event) { in r600_fence_ring_emit()
2566 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2599 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2635 * an interrupt if needed (r6xx-r7xx).
2641 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
2661 * other rings (r6xx-SI).
2704 * Copy GPU paging using the DMA engine (r6xx).
2706 * registered as the asic copy callback.
2714 int ring_index = rdev->asic->copy.dma_ring_index; in r600_copy_dma()
2722 DRM_ERROR("radeon: moving bo (%d).\n", r); in r600_copy_dma()
2730 DRM_ERROR("radeon: moving bo (%d).\n", r); in r600_copy_dma()
2814 rdev->asic->copy.copy = NULL; in r600_startup()
2825 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r600_startup()
2831 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in r600_startup()
2838 DRM_ERROR("radeon: IH init failed (%d).\n", r); in r600_startup()
2871 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r600_startup()
2904 * shape. in r600_resume()
2907 atom_asic_init(rdev->mode_info.atom_context); in r600_resume()
2934 * do nothing more than calling asic specific function. This
2936 * like vram_info.
2964 DRM_INFO("GPU not posted. posting now...\n"); in r600_init()
2965 atom_asic_init(rdev->mode_info.atom_context); in r600_init()
2994 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
2997 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; in r600_init()
3000 rdev->ih.ring_obj = NULL; in r600_init()
3021 /* Don't start up if the ucode is missing. */ in r600_init()
3023 DRM_ERROR("radeon: ucode required for R600+.\n"); in r600_init()
3067 } else if (rdev->wb.enabled) { in r600_ring_ib_execute()
3096 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); in r600_ib_test()
3102 DRM_ERROR("radeon: failed to get ib (%d).\n", r); in r600_ib_test()
3105 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in r600_ib_test()
3106 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_ib_test()
3107 ib.ptr[2] = 0xDEADBEEF; in r600_ib_test()
3108 ib.length_dw = 3; in r600_ib_test()
3111 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); in r600_ib_test()
3114 r = radeon_fence_wait(ib.fence, false); in r600_ib_test()
3116 DRM_ERROR("radeon: fence wait failed (%d).\n", r); in r600_ib_test()
3126 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); in r600_ib_test()
3145 * Test a simple IB in the DMA ring (r6xx-SI).
3146 * Returns 0 on success, error on failure.
3153 volatile uint32_t *ptr = rdev->vram_scratch.ptr; in r600_dma_ib_test()
3166 DRM_ERROR("radeon: failed to get ib (%d).\n", r); in r600_dma_ib_test()
3170 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); in r600_dma_ib_test()
3171 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; in r600_dma_ib_test()
3172 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; in r600_dma_ib_test()
3173 ib.ptr[3] = 0xDEADBEEF; in r600_dma_ib_test()
3174 ib.length_dw = 4; in r600_dma_ib_test()
3179 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); in r600_dma_ib_test()
3182 r = radeon_fence_wait(ib.fence, false); in r600_dma_ib_test()
3185 DRM_ERROR("radeon: fence wait failed (%d).\n", r); in r600_dma_ib_test()
3195 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); in r600_dma_ib_test()
3210 * Schedule an IB in the DMA ring (r6xx-r7xx).
3216 if (rdev->wb.enabled) { in r600_dma_ring_ib_execute()
3227 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. in r600_dma_ring_ib_execute()
3228 * Pad as necessary with NOPs. in r600_dma_ring_ib_execute()
3241 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3242 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3244 * and host consumes. As the host irq handler processes interrupts, it
3245 * increments the rptr. When the rptr catches up with the wptr, all the
3246 * current interrupts have been processed.
3256 rdev->ih.ring_size = ring_size; in r600_ih_ring_init()
3257 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3258 rdev->ih.rptr = 0; in r600_ih_ring_init()
3264 void *ring_ptr; /* FreeBSD: to please GCC 4.2. */ in r600_ih_ring_alloc()
3267 if (rdev->ih.ring_obj == NULL) { in r600_ih_ring_alloc()
3268 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
3271 NULL, &rdev->ih.ring_obj); in r600_ih_ring_alloc()
3273 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); in r600_ih_ring_alloc()
3276 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_alloc()
3278 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_alloc()
3281 r = radeon_bo_pin(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3283 &rdev->ih.gpu_addr); in r600_ih_ring_alloc()
3285 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3286 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_alloc()
3287 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); in r600_ih_ring_alloc()
3290 ring_ptr = &rdev->ih.ring; in r600_ih_ring_alloc()
3291 r = radeon_bo_kmap(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3294 radeon_bo_unpin(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3295 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3297 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); in r600_ih_ring_alloc()
3298 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_alloc()
3308 if (rdev->ih.ring_obj) { in r600_ih_ring_fini()
3309 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_fini()
3311 radeon_bo_kunmap(rdev->ih.ring_obj); in r600_ih_ring_fini()
3312 radeon_bo_unpin(rdev->ih.ring_obj); in r600_ih_ring_fini()
3313 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_fini()
3315 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_fini()
3316 rdev->ih.ring = NULL; in r600_ih_ring_fini()
3317 rdev->ih.ring_obj = NULL; in r600_ih_ring_fini()
3355 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in r600_rlc_init()
3356 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in r600_rlc_init()
3413 rdev->ih.enabled = true; in r600_enable_interrupts()
3428 rdev->ih.enabled = false; in r600_disable_interrupts()
3429 rdev->ih.rptr = 0; in r600_disable_interrupts()
3508 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3514 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ in r600_irq_init()
3518 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3519 rb_bufsz = drm_order(rdev->ih.ring_size / 4); in r600_irq_init()
3525 if (rdev->wb.enabled) in r600_irq_init()
3529 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3530 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3582 if (!rdev->irq.installed) { in r600_irq_set()
3587 if (!rdev->ih.enabled) { in r600_irq_set()
3617 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r600_irq_set()
3623 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in r600_irq_set()
3628 if (rdev->irq.crtc_vblank_int[0] || in r600_irq_set()
3629 atomic_read(&rdev->irq.pflip[0])) { in r600_irq_set()
3633 if (rdev->irq.crtc_vblank_int[1] || in r600_irq_set()
3634 atomic_read(&rdev->irq.pflip[1])) { in r600_irq_set()
3638 if (rdev->irq.hpd[0]) { in r600_irq_set()
3642 if (rdev->irq.hpd[1]) { in r600_irq_set()
3646 if (rdev->irq.hpd[2]) { in r600_irq_set()
3650 if (rdev->irq.hpd[3]) { in r600_irq_set()
3654 if (rdev->irq.hpd[4]) { in r600_irq_set()
3658 if (rdev->irq.hpd[5]) { in r600_irq_set()
3662 if (rdev->irq.afmt[0]) { in r600_irq_set()
3666 if (rdev->irq.afmt[1]) { in r600_irq_set()
3707 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3708 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3709 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3711 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3712 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3714 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3715 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3718 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3719 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3720 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3721 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3722 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3724 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3725 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3727 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3729 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3731 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3733 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3735 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3737 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3739 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3750 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3761 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3772 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3778 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3783 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
3788 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3793 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3799 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3804 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3831 if (rdev->wb.enabled) in r600_get_ih_wptr()
3832 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in r600_get_ih_wptr()
3838 * from the last not overwritten vector (wptr + 16). Hopefully in r600_get_ih_wptr()
3839 * this should allow us to catchup. in r600_get_ih_wptr()
3842 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); in r600_get_ih_wptr()
3843 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in r600_get_ih_wptr()
3848 return (wptr & rdev->ih.ptr_mask); in r600_get_ih_wptr()
3890 if (!rdev->ih.enabled || rdev->shutdown) in r600_irq_process()
3901 if (atomic_xchg(&rdev->ih.lock, 1)) in r600_irq_process()
3904 rptr = rdev->ih.rptr; in r600_irq_process()
3907 /* Order reading of wptr vs. reading of IH ring data */ in r600_irq_process()
3916 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in r600_irq_process()
3917 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in r600_irq_process()
3923 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { in r600_irq_process()
3924 if (rdev->irq.crtc_vblank_int[0]) { in r600_irq_process()
3926 rdev->pm.vblank_sync = true; in r600_irq_process()
3927 DRM_WAKEUP(&rdev->irq.vblank_queue); in r600_irq_process()
3929 if (atomic_read(&rdev->irq.pflip[0])) in r600_irq_process()
3931 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
3936 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { in r600_irq_process()
3937 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
3949 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { in r600_irq_process()
3950 if (rdev->irq.crtc_vblank_int[1]) { in r600_irq_process()
3952 rdev->pm.vblank_sync = true; in r600_irq_process()
3953 DRM_WAKEUP(&rdev->irq.vblank_queue); in r600_irq_process()
3955 if (atomic_read(&rdev->irq.pflip[1])) in r600_irq_process()
3957 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
3962 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { in r600_irq_process()
3963 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
3975 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_process()
3976 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
3982 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_process()
3983 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
3989 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_process()
3990 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
3996 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_process()
3997 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
4003 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_process()
4004 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
4010 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_process()
4011 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
4024 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_process()
4025 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4031 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_process()
4032 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4066 rptr &= rdev->ih.ptr_mask; in r600_irq_process()
4072 rdev->ih.rptr = rptr; in r600_irq_process()
4073 WREG32(IH_RB_RPTR, rdev->ih.rptr); in r600_irq_process()
4074 atomic_set(&rdev->ih.lock, 0); in r600_irq_process()
4121 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4122 * directly perform HDP flush by writing register through MMIO.
4126 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read in r600_ioctl_wait_idle()
4127 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. in r600_ioctl_wait_idle()
4128 * This seems to cause problems on some AGP cards. Just use the old in r600_ioctl_wait_idle()
4129 * method for them. in r600_ioctl_wait_idle()
4132 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { in r600_ioctl_wait_idle()
4133 volatile uint32_t *ptr = rdev->vram_scratch.ptr; in r600_ioctl_wait_idle()
4201 …* a complete re-config. … in r600_set_pcie_lanes()
4202 …* e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) … in r600_set_pcie_lanes()
4296 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); in r600_pcie_gen2_enable()
4383 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4384 * Returns the 64 bit clock counter snapshot.