Lines Matching refs:src_reloc
2891 struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc; in evergreen_dma_cs_parse() local
2940 r = r600_dma_cs_next_reloc(p, &src_reloc); in evergreen_dma_cs_parse()
2971 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2973 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2988 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2989 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3001 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); in evergreen_dma_cs_parse()
3007 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3008 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3031 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3033 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3048 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3049 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3059 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); in evergreen_dma_cs_parse()
3069 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3070 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3076 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3078 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3094 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); in evergreen_dma_cs_parse()
3115 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3117 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3132 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3133 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3148 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); in evergreen_dma_cs_parse()
3158 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3159 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3165 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3167 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3191 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3193 (uintmax_t)src_offset + count, radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3202 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
3204 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3213 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
3214 ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3233 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3235 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3250 ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3253 ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3266 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3268 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3277 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3279 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in evergreen_dma_cs_parse()