Lines Matching refs:scratch_addr
183 u32 scratch_addr = pc->gtt_offset + 128; in intel_emit_post_sync_nonzero_flush() local
194 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ in intel_emit_post_sync_nonzero_flush()
206 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ in intel_emit_post_sync_nonzero_flush()
221 u32 scratch_addr = pc->gtt_offset + 128; in gen6_render_ring_flush() local
261 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); in gen6_render_ring_flush()
293 u32 scratch_addr = pc->gtt_offset + 128; in gen7_render_ring_flush() local
338 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); in gen7_render_ring_flush()
677 u32 scratch_addr = pc->gtt_offset + 128; in pc_render_add_request() local
698 PIPE_CONTROL_FLUSH(ring, scratch_addr); in pc_render_add_request()
699 scratch_addr += 128; /* write to separate cachelines */ in pc_render_add_request()
700 PIPE_CONTROL_FLUSH(ring, scratch_addr); in pc_render_add_request()
701 scratch_addr += 128; in pc_render_add_request()
702 PIPE_CONTROL_FLUSH(ring, scratch_addr); in pc_render_add_request()
703 scratch_addr += 128; in pc_render_add_request()
704 PIPE_CONTROL_FLUSH(ring, scratch_addr); in pc_render_add_request()
705 scratch_addr += 128; in pc_render_add_request()
706 PIPE_CONTROL_FLUSH(ring, scratch_addr); in pc_render_add_request()
707 scratch_addr += 128; in pc_render_add_request()
708 PIPE_CONTROL_FLUSH(ring, scratch_addr); in pc_render_add_request()