2300 struct mtx mchdev_lock;  variable
2301 MTX_SYSINIT(mchdev, &mchdev_lock, "mchdev", MTX_DEF);
2312 	mtx_assert(&mchdev_lock, MA_OWNED);  in ironlake_set_drps()
2337 	mtx_lock(&mchdev_lock);  in ironlake_enable_drps()
2396 	mtx_unlock(&mchdev_lock);  in ironlake_enable_drps()
2404 	mtx_lock(&mchdev_lock);  in ironlake_disable_drps()
2422 	mtx_unlock(&mchdev_lock);  in ironlake_disable_drps()
2876 	mtx_assert(&mchdev_lock, MA_OWNED);  in __i915_chipset_val()
2930 	mtx_lock(&mchdev_lock);  in i915_chipset_val()
2934 	mtx_unlock(&mchdev_lock);  in i915_chipset_val()
3102 	mtx_assert(&mchdev_lock, MA_OWNED);  in __i915_update_gfx_val()
3135 	mtx_lock(&mchdev_lock);  in i915_update_gfx_val()
3139 	mtx_unlock(&mchdev_lock);  in i915_update_gfx_val()
3147 	mtx_assert(&mchdev_lock, MA_OWNED);  in __i915_gfx_val()
3186 	mtx_lock(&mchdev_lock);  in i915_gfx_val()
3190 	mtx_unlock(&mchdev_lock);  in i915_gfx_val()
3206 	mtx_lock(&mchdev_lock);  in i915_read_mch_val()
3217 	mtx_unlock(&mchdev_lock);  in i915_read_mch_val()
3233 	mtx_lock(&mchdev_lock);  in i915_gpu_raise()
3244 	mtx_unlock(&mchdev_lock);  in i915_gpu_raise()
3261 	mtx_lock(&mchdev_lock);  in i915_gpu_lower()
3272 	mtx_unlock(&mchdev_lock);  in i915_gpu_lower()
3290 	mtx_lock(&mchdev_lock);  in i915_gpu_busy()
3299 	mtx_unlock(&mchdev_lock);  in i915_gpu_busy()
3316 	mtx_lock(&mchdev_lock);  in i915_gpu_turbo_disable()
3329 	mtx_unlock(&mchdev_lock);  in i915_gpu_turbo_disable()
3361 	mtx_lock(&mchdev_lock);  in intel_gpu_ips_init()
3363 	mtx_unlock(&mchdev_lock);  in intel_gpu_ips_init()
3372 	mtx_lock(&mchdev_lock);  in intel_gpu_ips_teardown()
3374 	mtx_unlock(&mchdev_lock);  in intel_gpu_ips_teardown()