Lines Matching refs:ips
609 dev_priv->ips.r_t = dev_priv->mem_freq; in i915_ironlake_get_mem_freq()
641 dev_priv->ips.c_m = 0; in i915_ironlake_get_mem_freq()
643 dev_priv->ips.c_m = 1; in i915_ironlake_get_mem_freq()
645 dev_priv->ips.c_m = 2; in i915_ironlake_get_mem_freq()
2362 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ in ironlake_enable_drps()
2363 dev_priv->ips.fstart = fstart; in ironlake_enable_drps()
2365 dev_priv->ips.max_delay = fstart; in ironlake_enable_drps()
2366 dev_priv->ips.min_delay = fmin; in ironlake_enable_drps()
2367 dev_priv->ips.cur_delay = fstart; in ironlake_enable_drps()
2390 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + in ironlake_enable_drps()
2392 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); in ironlake_enable_drps()
2393 dev_priv->ips.last_count2 = I915_READ(0x112f4); in ironlake_enable_drps()
2394 getrawmonotonic(&dev_priv->ips.last_time2); in ironlake_enable_drps()
2416 ironlake_set_drps(dev, dev_priv->ips.fstart); in ironlake_disable_drps()
2728 if (dev_priv->ips.renderctx) { in ironlake_teardown_rc6()
2729 i915_gem_object_unpin(dev_priv->ips.renderctx); in ironlake_teardown_rc6()
2730 drm_gem_object_unreference(&dev_priv->ips.renderctx->base); in ironlake_teardown_rc6()
2731 dev_priv->ips.renderctx = NULL; in ironlake_teardown_rc6()
2734 if (dev_priv->ips.pwrctx) { in ironlake_teardown_rc6()
2735 i915_gem_object_unpin(dev_priv->ips.pwrctx); in ironlake_teardown_rc6()
2736 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); in ironlake_teardown_rc6()
2737 dev_priv->ips.pwrctx = NULL; in ironlake_teardown_rc6()
2763 if (dev_priv->ips.renderctx == NULL) in ironlake_setup_rc6()
2764 dev_priv->ips.renderctx = intel_alloc_context_page(dev); in ironlake_setup_rc6()
2765 if (!dev_priv->ips.renderctx) in ironlake_setup_rc6()
2768 if (dev_priv->ips.pwrctx == NULL) in ironlake_setup_rc6()
2769 dev_priv->ips.pwrctx = intel_alloc_context_page(dev); in ironlake_setup_rc6()
2770 if (!dev_priv->ips.pwrctx) { in ironlake_setup_rc6()
2813 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | in ironlake_enable_rc6()
2836 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); in ironlake_enable_rc6()
2878 diff1 = now - dev_priv->ips.last_time1; in __i915_chipset_val()
2886 return dev_priv->ips.chipset_power; in __i915_chipset_val()
2895 if (total_count < dev_priv->ips.last_count1) { in __i915_chipset_val()
2896 diff = ~0UL - dev_priv->ips.last_count1; in __i915_chipset_val()
2899 diff = total_count - dev_priv->ips.last_count1; in __i915_chipset_val()
2903 if (cparams[i].i == dev_priv->ips.c_m && in __i915_chipset_val()
2904 cparams[i].t == dev_priv->ips.r_t) { in __i915_chipset_val()
2915 dev_priv->ips.last_count1 = total_count; in __i915_chipset_val()
2916 dev_priv->ips.last_time1 = now; in __i915_chipset_val()
2918 dev_priv->ips.chipset_power = ret; in __i915_chipset_val()
3105 timespecsub(&now, &dev_priv->ips.last_time2, &diff1); in __i915_update_gfx_val()
3114 if (count < dev_priv->ips.last_count2) { in __i915_update_gfx_val()
3115 diff = ~0UL - dev_priv->ips.last_count2; in __i915_update_gfx_val()
3118 diff = count - dev_priv->ips.last_count2; in __i915_update_gfx_val()
3121 dev_priv->ips.last_count2 = count; in __i915_update_gfx_val()
3122 dev_priv->ips.last_time2 = now; in __i915_update_gfx_val()
3127 dev_priv->ips.gfx_power = diff; in __i915_update_gfx_val()
3169 corr2 = (corr * dev_priv->ips.corr); in __i915_gfx_val()
3176 return dev_priv->ips.gfx_power + state2; in __i915_gfx_val()
3240 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) in i915_gpu_raise()
3241 dev_priv->ips.max_delay--; in i915_gpu_raise()
3268 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) in i915_gpu_lower()
3269 dev_priv->ips.max_delay++; in i915_gpu_lower()
3323 dev_priv->ips.max_delay = dev_priv->ips.fstart; in i915_gpu_turbo_disable()
3325 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) in i915_gpu_turbo_disable()
3444 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); in intel_init_emon()