Lines Matching refs:dev_priv
60 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_disable_fbc() local
83 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_enable_fbc() local
92 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; in i8xx_enable_fbc()
125 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_fbc_enabled() local
133 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_enable_fbc() local
159 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_disable_fbc() local
174 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_fbc_enabled() local
181 struct drm_i915_private *dev_priv = dev->dev_private; in sandybridge_blit_fbc_update() local
185 gen6_gt_force_wake_get(dev_priv); in sandybridge_blit_fbc_update()
196 gen6_gt_force_wake_put(dev_priv); in sandybridge_blit_fbc_update()
202 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_enable_fbc() local
239 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_disable_fbc() local
254 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fbc_enabled() local
261 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fbc_enabled() local
263 if (!dev_priv->display.fbc_enabled) in intel_fbc_enabled()
266 return dev_priv->display.fbc_enabled(dev); in intel_fbc_enabled()
273 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fbc_work_fn() local
276 if (work == dev_priv->fbc_work) { in intel_fbc_work_fn()
281 dev_priv->display.enable_fbc(work->crtc, in intel_fbc_work_fn()
284 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; in intel_fbc_work_fn()
285 dev_priv->cfb_fb = work->crtc->fb->base.id; in intel_fbc_work_fn()
286 dev_priv->cfb_y = work->crtc->y; in intel_fbc_work_fn()
289 dev_priv->fbc_work = NULL; in intel_fbc_work_fn()
296 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) in intel_cancel_fbc_work() argument
298 if (dev_priv->fbc_work == NULL) in intel_cancel_fbc_work()
307 if (taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->fbc_work->work, in intel_cancel_fbc_work()
310 free(dev_priv->fbc_work, DRM_MEM_KMS); in intel_cancel_fbc_work()
317 dev_priv->fbc_work = NULL; in intel_cancel_fbc_work()
324 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_fbc() local
326 if (!dev_priv->display.enable_fbc) in intel_enable_fbc()
329 intel_cancel_fbc_work(dev_priv); in intel_enable_fbc()
333 dev_priv->display.enable_fbc(crtc, interval); in intel_enable_fbc()
340 TIMEOUT_TASK_INIT(dev_priv->wq, &work->work, 0, intel_fbc_work_fn, in intel_enable_fbc()
343 dev_priv->fbc_work = work; in intel_enable_fbc()
358 taskqueue_enqueue_timeout(dev_priv->wq, &work->work, in intel_enable_fbc()
364 struct drm_i915_private *dev_priv = dev->dev_private; in intel_disable_fbc() local
366 intel_cancel_fbc_work(dev_priv); in intel_disable_fbc()
368 if (!dev_priv->display.disable_fbc) in intel_disable_fbc()
371 dev_priv->display.disable_fbc(dev); in intel_disable_fbc()
372 dev_priv->cfb_plane = -1; in intel_disable_fbc()
396 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_fbc() local
424 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; in intel_update_fbc()
433 dev_priv->no_fbc_reason = FBC_NO_OUTPUT; in intel_update_fbc()
451 dev_priv->no_fbc_reason = FBC_MODULE_PARAM; in intel_update_fbc()
454 if (intel_fb->obj->base.size > dev_priv->cfb_size) { in intel_update_fbc()
457 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; in intel_update_fbc()
464 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; in intel_update_fbc()
470 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; in intel_update_fbc()
475 dev_priv->no_fbc_reason = FBC_BAD_PLANE; in intel_update_fbc()
485 dev_priv->no_fbc_reason = FBC_NOT_TILED; in intel_update_fbc()
498 if (dev_priv->cfb_plane == intel_crtc->plane && in intel_update_fbc()
499 dev_priv->cfb_fb == fb->base.id && in intel_update_fbc()
500 dev_priv->cfb_y == crtc->y) in intel_update_fbc()
544 drm_i915_private_t *dev_priv = dev->dev_private; in i915_pineview_get_mem_freq() local
551 dev_priv->fsb_freq = 533; /* 133*4 */ in i915_pineview_get_mem_freq()
554 dev_priv->fsb_freq = 800; /* 200*4 */ in i915_pineview_get_mem_freq()
557 dev_priv->fsb_freq = 667; /* 167*4 */ in i915_pineview_get_mem_freq()
560 dev_priv->fsb_freq = 400; /* 100*4 */ in i915_pineview_get_mem_freq()
566 dev_priv->mem_freq = 533; in i915_pineview_get_mem_freq()
569 dev_priv->mem_freq = 667; in i915_pineview_get_mem_freq()
572 dev_priv->mem_freq = 800; in i915_pineview_get_mem_freq()
578 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; in i915_pineview_get_mem_freq()
583 drm_i915_private_t *dev_priv = dev->dev_private; in i915_ironlake_get_mem_freq() local
591 dev_priv->mem_freq = 800; in i915_ironlake_get_mem_freq()
594 dev_priv->mem_freq = 1066; in i915_ironlake_get_mem_freq()
597 dev_priv->mem_freq = 1333; in i915_ironlake_get_mem_freq()
600 dev_priv->mem_freq = 1600; in i915_ironlake_get_mem_freq()
605 dev_priv->mem_freq = 0; in i915_ironlake_get_mem_freq()
609 dev_priv->ips.r_t = dev_priv->mem_freq; in i915_ironlake_get_mem_freq()
613 dev_priv->fsb_freq = 3200; in i915_ironlake_get_mem_freq()
616 dev_priv->fsb_freq = 3733; in i915_ironlake_get_mem_freq()
619 dev_priv->fsb_freq = 4266; in i915_ironlake_get_mem_freq()
622 dev_priv->fsb_freq = 4800; in i915_ironlake_get_mem_freq()
625 dev_priv->fsb_freq = 5333; in i915_ironlake_get_mem_freq()
628 dev_priv->fsb_freq = 5866; in i915_ironlake_get_mem_freq()
631 dev_priv->fsb_freq = 6400; in i915_ironlake_get_mem_freq()
636 dev_priv->fsb_freq = 0; in i915_ironlake_get_mem_freq()
640 if (dev_priv->fsb_freq == 3200) { in i915_ironlake_get_mem_freq()
641 dev_priv->ips.c_m = 0; in i915_ironlake_get_mem_freq()
642 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { in i915_ironlake_get_mem_freq()
643 dev_priv->ips.c_m = 1; in i915_ironlake_get_mem_freq()
645 dev_priv->ips.c_m = 2; in i915_ironlake_get_mem_freq()
713 struct drm_i915_private *dev_priv = dev->dev_private; in pineview_disable_cxsr() local
737 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_fifo_size() local
753 struct drm_i915_private *dev_priv = dev->dev_private; in i85x_get_fifo_size() local
770 struct drm_i915_private *dev_priv = dev->dev_private; in i845_get_fifo_size() local
786 struct drm_i915_private *dev_priv = dev->dev_private; in i830_get_fifo_size() local
1018 struct drm_i915_private *dev_priv = dev->dev_private; in pineview_update_wm() local
1024 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, in pineview_update_wm()
1025 dev_priv->fsb_freq, dev_priv->mem_freq); in pineview_update_wm()
1259 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_update_drain_latency() local
1297 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_update_wm() local
1356 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_update_wm() local
1407 struct drm_i915_private *dev_priv = dev->dev_private; in i965_update_wm() local
1472 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_update_wm() local
1488 fifo_size = dev_priv->display.get_fifo_size(dev, 0); in i9xx_update_wm()
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 1); in i9xx_update_wm()
1589 struct drm_i915_private *dev_priv = dev->dev_private; in i830_update_wm() local
1599 dev_priv->display.get_fifo_size(dev, 0), in i830_update_wm()
1624 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_check_srwm() local
1715 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_update_wm() local
1798 struct drm_i915_private *dev_priv = dev->dev_private; in sandybridge_update_wm() local
1848 dev_priv->sprite_scaling_enabled) in sandybridge_update_wm()
1900 struct drm_i915_private *dev_priv = dev->dev_private; in ivybridge_update_wm() local
1965 dev_priv->sprite_scaling_enabled) in ivybridge_update_wm()
2024 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_update_linetime_wm() local
2126 struct drm_i915_private *dev_priv = dev->dev_private; in sandybridge_update_sprite_wm() local
2236 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_watermarks() local
2238 if (dev_priv->display.update_wm) in intel_update_watermarks()
2239 dev_priv->display.update_wm(dev); in intel_update_watermarks()
2245 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_linetime_watermarks() local
2247 if (dev_priv->display.update_linetime_wm) in intel_update_linetime_watermarks()
2248 dev_priv->display.update_linetime_wm(dev, pipe, mode); in intel_update_linetime_watermarks()
2254 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_sprite_watermarks() local
2256 if (dev_priv->display.update_sprite_wm) in intel_update_sprite_watermarks()
2257 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, in intel_update_sprite_watermarks()
2309 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_set_drps() local
2333 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_enable_drps() local
2362 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ in ironlake_enable_drps()
2363 dev_priv->ips.fstart = fstart; in ironlake_enable_drps()
2365 dev_priv->ips.max_delay = fstart; in ironlake_enable_drps()
2366 dev_priv->ips.min_delay = fmin; in ironlake_enable_drps()
2367 dev_priv->ips.cur_delay = fstart; in ironlake_enable_drps()
2390 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + in ironlake_enable_drps()
2392 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); in ironlake_enable_drps()
2393 dev_priv->ips.last_count2 = I915_READ(0x112f4); in ironlake_enable_drps()
2394 getrawmonotonic(&dev_priv->ips.last_time2); in ironlake_enable_drps()
2401 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_disable_drps() local
2416 ironlake_set_drps(dev, dev_priv->ips.fstart); in ironlake_disable_drps()
2430 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) in gen6_rps_limits() argument
2436 if (*val >= dev_priv->rps.max_delay) in gen6_rps_limits()
2437 *val = dev_priv->rps.max_delay; in gen6_rps_limits()
2438 limits |= dev_priv->rps.max_delay << 24; in gen6_rps_limits()
2446 if (*val <= dev_priv->rps.min_delay) { in gen6_rps_limits()
2447 *val = dev_priv->rps.min_delay; in gen6_rps_limits()
2448 limits |= dev_priv->rps.min_delay << 16; in gen6_rps_limits()
2456 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_set_rps() local
2457 u32 limits = gen6_rps_limits(dev_priv, &val); in gen6_set_rps()
2459 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED); in gen6_set_rps()
2460 WARN_ON(val > dev_priv->rps.max_delay); in gen6_set_rps()
2461 WARN_ON(val < dev_priv->rps.min_delay); in gen6_set_rps()
2463 if (val == dev_priv->rps.cur_delay) in gen6_set_rps()
2478 dev_priv->rps.cur_delay = val; in gen6_set_rps()
2483 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_disable_rps() local
2494 mtx_lock(&dev_priv->rps.lock); in gen6_disable_rps()
2495 dev_priv->rps.pm_iir = 0; in gen6_disable_rps()
2496 mtx_unlock(&dev_priv->rps.lock); in gen6_disable_rps()
2528 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_enable_rps() local
2537 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED); in gen6_enable_rps()
2553 gen6_gt_force_wake_get(dev_priv); in gen6_enable_rps()
2559 dev_priv->rps.max_delay = rp_state_cap & 0xff; in gen6_enable_rps()
2560 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; in gen6_enable_rps()
2561 dev_priv->rps.cur_delay = 0; in gen6_enable_rps()
2572 for_each_ring(ring, dev_priv, i) in gen6_enable_rps()
2582 rc6_mode = intel_enable_rc6(dev_priv->dev); in gen6_enable_rps()
2614 dev_priv->rps.max_delay << 24 | in gen6_enable_rps()
2615 dev_priv->rps.min_delay << 16); in gen6_enable_rps()
2631 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); in gen6_enable_rps()
2634 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); in gen6_enable_rps()
2636 dev_priv->rps.max_delay = pcu_mbox & 0xff; in gen6_enable_rps()
2643 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); in gen6_enable_rps()
2647 mtx_lock(&dev_priv->rps.lock); in gen6_enable_rps()
2648 WARN_ON(dev_priv->rps.pm_iir != 0); in gen6_enable_rps()
2650 mtx_unlock(&dev_priv->rps.lock); in gen6_enable_rps()
2655 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); in gen6_enable_rps()
2663 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); in gen6_enable_rps()
2668 gen6_gt_force_wake_put(dev_priv); in gen6_enable_rps()
2673 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_update_ring_freq() local
2679 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED); in gen6_update_ring_freq()
2703 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; in gen6_update_ring_freq()
2705 int diff = dev_priv->rps.max_delay - gpu_freq; in gen6_update_ring_freq()
2718 sandybridge_pcode_write(dev_priv, in gen6_update_ring_freq()
2726 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_teardown_rc6() local
2728 if (dev_priv->ips.renderctx) { in ironlake_teardown_rc6()
2729 i915_gem_object_unpin(dev_priv->ips.renderctx); in ironlake_teardown_rc6()
2730 drm_gem_object_unreference(&dev_priv->ips.renderctx->base); in ironlake_teardown_rc6()
2731 dev_priv->ips.renderctx = NULL; in ironlake_teardown_rc6()
2734 if (dev_priv->ips.pwrctx) { in ironlake_teardown_rc6()
2735 i915_gem_object_unpin(dev_priv->ips.pwrctx); in ironlake_teardown_rc6()
2736 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); in ironlake_teardown_rc6()
2737 dev_priv->ips.pwrctx = NULL; in ironlake_teardown_rc6()
2743 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_disable_rc6() local
2761 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_setup_rc6() local
2763 if (dev_priv->ips.renderctx == NULL) in ironlake_setup_rc6()
2764 dev_priv->ips.renderctx = intel_alloc_context_page(dev); in ironlake_setup_rc6()
2765 if (!dev_priv->ips.renderctx) in ironlake_setup_rc6()
2768 if (dev_priv->ips.pwrctx == NULL) in ironlake_setup_rc6()
2769 dev_priv->ips.pwrctx = intel_alloc_context_page(dev); in ironlake_setup_rc6()
2770 if (!dev_priv->ips.pwrctx) { in ironlake_setup_rc6()
2780 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_enable_rc6() local
2781 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; in ironlake_enable_rc6()
2797 was_interruptible = dev_priv->mm.interruptible; in ironlake_enable_rc6()
2798 dev_priv->mm.interruptible = false; in ironlake_enable_rc6()
2807 dev_priv->mm.interruptible = was_interruptible; in ironlake_enable_rc6()
2813 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | in ironlake_enable_rc6()
2829 dev_priv->mm.interruptible = was_interruptible; in ironlake_enable_rc6()
2836 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); in ironlake_enable_rc6()
2869 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) in __i915_chipset_val() argument
2878 diff1 = now - dev_priv->ips.last_time1; in __i915_chipset_val()
2886 return dev_priv->ips.chipset_power; in __i915_chipset_val()
2895 if (total_count < dev_priv->ips.last_count1) { in __i915_chipset_val()
2896 diff = ~0UL - dev_priv->ips.last_count1; in __i915_chipset_val()
2899 diff = total_count - dev_priv->ips.last_count1; in __i915_chipset_val()
2903 if (cparams[i].i == dev_priv->ips.c_m && in __i915_chipset_val()
2904 cparams[i].t == dev_priv->ips.r_t) { in __i915_chipset_val()
2915 dev_priv->ips.last_count1 = total_count; in __i915_chipset_val()
2916 dev_priv->ips.last_time1 = now; in __i915_chipset_val()
2918 dev_priv->ips.chipset_power = ret; in __i915_chipset_val()
2923 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) in i915_chipset_val() argument
2927 if (dev_priv->info->gen != 5) in i915_chipset_val()
2932 val = __i915_chipset_val(dev_priv); in i915_chipset_val()
2939 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) in i915_mch_val() argument
2954 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) in pvid_to_extvid() argument
3089 if (dev_priv->info->is_mobile) in pvid_to_extvid()
3095 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) in __i915_update_gfx_val() argument
3105 timespecsub(&now, &dev_priv->ips.last_time2, &diff1); in __i915_update_gfx_val()
3114 if (count < dev_priv->ips.last_count2) { in __i915_update_gfx_val()
3115 diff = ~0UL - dev_priv->ips.last_count2; in __i915_update_gfx_val()
3118 diff = count - dev_priv->ips.last_count2; in __i915_update_gfx_val()
3121 dev_priv->ips.last_count2 = count; in __i915_update_gfx_val()
3122 dev_priv->ips.last_time2 = now; in __i915_update_gfx_val()
3127 dev_priv->ips.gfx_power = diff; in __i915_update_gfx_val()
3130 void i915_update_gfx_val(struct drm_i915_private *dev_priv) in i915_update_gfx_val() argument
3132 if (dev_priv->info->gen != 5) in i915_update_gfx_val()
3137 __i915_update_gfx_val(dev_priv); in i915_update_gfx_val()
3142 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) in __i915_gfx_val() argument
3149 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); in __i915_gfx_val()
3151 ext_v = pvid_to_extvid(dev_priv, pxvid); in __i915_gfx_val()
3155 t = i915_mch_val(dev_priv); in __i915_gfx_val()
3169 corr2 = (corr * dev_priv->ips.corr); in __i915_gfx_val()
3174 __i915_update_gfx_val(dev_priv); in __i915_gfx_val()
3176 return dev_priv->ips.gfx_power + state2; in __i915_gfx_val()
3179 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) in i915_gfx_val() argument
3183 if (dev_priv->info->gen != 5) in i915_gfx_val()
3188 val = __i915_gfx_val(dev_priv); in i915_gfx_val()
3203 struct drm_i915_private *dev_priv; in i915_read_mch_val() local
3209 dev_priv = i915_mch_dev; in i915_read_mch_val()
3211 chipset_val = __i915_chipset_val(dev_priv); in i915_read_mch_val()
3212 graphics_val = __i915_gfx_val(dev_priv); in i915_read_mch_val()
3230 struct drm_i915_private *dev_priv; in i915_gpu_raise() local
3238 dev_priv = i915_mch_dev; in i915_gpu_raise()
3240 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) in i915_gpu_raise()
3241 dev_priv->ips.max_delay--; in i915_gpu_raise()
3258 struct drm_i915_private *dev_priv; in i915_gpu_lower() local
3266 dev_priv = i915_mch_dev; in i915_gpu_lower()
3268 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) in i915_gpu_lower()
3269 dev_priv->ips.max_delay++; in i915_gpu_lower()
3285 struct drm_i915_private *dev_priv; in i915_gpu_busy() local
3293 dev_priv = i915_mch_dev; in i915_gpu_busy()
3295 for_each_ring(ring, dev_priv, i) in i915_gpu_busy()
3313 struct drm_i915_private *dev_priv; in i915_gpu_turbo_disable() local
3321 dev_priv = i915_mch_dev; in i915_gpu_turbo_disable()
3323 dev_priv->ips.max_delay = dev_priv->ips.fstart; in i915_gpu_turbo_disable()
3325 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) in i915_gpu_turbo_disable()
3357 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) in intel_gpu_ips_init() argument
3362 i915_mch_dev = dev_priv; in intel_gpu_ips_init()
3378 struct drm_i915_private *dev_priv = dev->dev_private; in intel_init_emon() local
3444 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); in intel_init_emon()
3449 struct drm_i915_private *dev_priv = dev->dev_private; in intel_disable_gt_powersave() local
3455 taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->rps.delayed_resume_work, NULL); in intel_disable_gt_powersave()
3456 sx_xlock(&dev_priv->rps.hw_lock); in intel_disable_gt_powersave()
3458 sx_xunlock(&dev_priv->rps.hw_lock); in intel_disable_gt_powersave()
3464 struct drm_i915_private *dev_priv = arg; in intel_gen6_powersave_work() local
3465 struct drm_device *dev = dev_priv->dev; in intel_gen6_powersave_work()
3467 sx_xlock(&dev_priv->rps.hw_lock); in intel_gen6_powersave_work()
3470 sx_xunlock(&dev_priv->rps.hw_lock); in intel_gen6_powersave_work()
3475 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_gt_powersave() local
3487 taskqueue_enqueue_timeout(dev_priv->wq, &dev_priv->rps.delayed_resume_work, in intel_enable_gt_powersave()
3494 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_init_clock_gating() local
3506 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_init_clock_gating() local
3572 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_init_clock_gating() local
3589 if (dev_priv->fdi_rx_polarity_inverted) in cpt_init_clock_gating()
3602 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_init_clock_gating() local
3713 intel_flush_display_plane(dev_priv, pipe); in gen6_init_clock_gating()
3724 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) in gen7_setup_fixed_func_scheduler() argument
3738 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_init_clock_gating() local
3744 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) in lpt_init_clock_gating()
3752 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_init_clock_gating() local
3783 intel_flush_display_plane(dev_priv, pipe); in haswell_init_clock_gating()
3786 gen7_setup_fixed_func_scheduler(dev_priv); in haswell_init_clock_gating()
3810 struct drm_i915_private *dev_priv = dev->dev_private; in ivybridge_init_clock_gating() local
3884 intel_flush_display_plane(dev_priv, pipe); in ivybridge_init_clock_gating()
3891 gen7_setup_fixed_func_scheduler(dev_priv); in ivybridge_init_clock_gating()
3907 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_init_clock_gating() local
3987 intel_flush_display_plane(dev_priv, pipe); in valleyview_init_clock_gating()
4016 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_init_clock_gating() local
4038 struct drm_i915_private *dev_priv = dev->dev_private; in crestline_init_clock_gating() local
4049 struct drm_i915_private *dev_priv = dev->dev_private; in broadwater_init_clock_gating() local
4061 struct drm_i915_private *dev_priv = dev->dev_private; in gen3_init_clock_gating() local
4077 struct drm_i915_private *dev_priv = dev->dev_private; in i85x_init_clock_gating() local
4084 struct drm_i915_private *dev_priv = dev->dev_private; in i830_init_clock_gating() local
4091 struct drm_i915_private *dev_priv = dev->dev_private; in intel_init_clock_gating() local
4093 dev_priv->display.init_clock_gating(dev); in intel_init_clock_gating()
4101 struct drm_i915_private *dev_priv = dev->dev_private; in intel_init_power_wells() local
4130 struct drm_i915_private *dev_priv = dev->dev_private; in intel_init_pm() local
4134 dev_priv->display.fbc_enabled = ironlake_fbc_enabled; in intel_init_pm()
4135 dev_priv->display.enable_fbc = ironlake_enable_fbc; in intel_init_pm()
4136 dev_priv->display.disable_fbc = ironlake_disable_fbc; in intel_init_pm()
4138 dev_priv->display.fbc_enabled = g4x_fbc_enabled; in intel_init_pm()
4139 dev_priv->display.enable_fbc = g4x_enable_fbc; in intel_init_pm()
4140 dev_priv->display.disable_fbc = g4x_disable_fbc; in intel_init_pm()
4142 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; in intel_init_pm()
4143 dev_priv->display.enable_fbc = i8xx_enable_fbc; in intel_init_pm()
4144 dev_priv->display.disable_fbc = i8xx_disable_fbc; in intel_init_pm()
4159 dev_priv->display.update_wm = ironlake_update_wm; in intel_init_pm()
4163 dev_priv->display.update_wm = NULL; in intel_init_pm()
4165 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; in intel_init_pm()
4168 dev_priv->display.update_wm = sandybridge_update_wm; in intel_init_pm()
4169 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; in intel_init_pm()
4173 dev_priv->display.update_wm = NULL; in intel_init_pm()
4175 dev_priv->display.init_clock_gating = gen6_init_clock_gating; in intel_init_pm()
4179 dev_priv->display.update_wm = ivybridge_update_wm; in intel_init_pm()
4180 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; in intel_init_pm()
4184 dev_priv->display.update_wm = NULL; in intel_init_pm()
4186 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; in intel_init_pm()
4189 dev_priv->display.update_wm = sandybridge_update_wm; in intel_init_pm()
4190 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; in intel_init_pm()
4191 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; in intel_init_pm()
4195 dev_priv->display.update_wm = NULL; in intel_init_pm()
4197 dev_priv->display.init_clock_gating = haswell_init_clock_gating; in intel_init_pm()
4199 dev_priv->display.update_wm = NULL; in intel_init_pm()
4201 dev_priv->display.update_wm = valleyview_update_wm; in intel_init_pm()
4202 dev_priv->display.init_clock_gating = in intel_init_pm()
4206 dev_priv->is_ddr3, in intel_init_pm()
4207 dev_priv->fsb_freq, in intel_init_pm()
4208 dev_priv->mem_freq)) { in intel_init_pm()
4212 (dev_priv->is_ddr3 == 1) ? "3" : "2", in intel_init_pm()
4213 dev_priv->fsb_freq, dev_priv->mem_freq); in intel_init_pm()
4216 dev_priv->display.update_wm = NULL; in intel_init_pm()
4218 dev_priv->display.update_wm = pineview_update_wm; in intel_init_pm()
4219 dev_priv->display.init_clock_gating = gen3_init_clock_gating; in intel_init_pm()
4221 dev_priv->display.update_wm = g4x_update_wm; in intel_init_pm()
4222 dev_priv->display.init_clock_gating = g4x_init_clock_gating; in intel_init_pm()
4224 dev_priv->display.update_wm = i965_update_wm; in intel_init_pm()
4226 dev_priv->display.init_clock_gating = crestline_init_clock_gating; in intel_init_pm()
4228 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; in intel_init_pm()
4230 dev_priv->display.update_wm = i9xx_update_wm; in intel_init_pm()
4231 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; in intel_init_pm()
4232 dev_priv->display.init_clock_gating = gen3_init_clock_gating; in intel_init_pm()
4234 dev_priv->display.update_wm = i830_update_wm; in intel_init_pm()
4235 dev_priv->display.init_clock_gating = i85x_init_clock_gating; in intel_init_pm()
4236 dev_priv->display.get_fifo_size = i830_get_fifo_size; in intel_init_pm()
4238 dev_priv->display.update_wm = i9xx_update_wm; in intel_init_pm()
4239 dev_priv->display.get_fifo_size = i85x_get_fifo_size; in intel_init_pm()
4240 dev_priv->display.init_clock_gating = i85x_init_clock_gating; in intel_init_pm()
4242 dev_priv->display.update_wm = i830_update_wm; in intel_init_pm()
4243 dev_priv->display.init_clock_gating = i830_init_clock_gating; in intel_init_pm()
4245 dev_priv->display.get_fifo_size = i845_get_fifo_size; in intel_init_pm()
4247 dev_priv->display.get_fifo_size = i830_get_fifo_size; in intel_init_pm()
4251 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) in __gen6_gt_wait_for_thread_c0() argument
4255 if (IS_HASWELL(dev_priv->dev)) in __gen6_gt_wait_for_thread_c0()
4267 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) in __gen6_gt_force_wake_reset() argument
4273 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) in __gen6_gt_force_wake_get() argument
4277 if (IS_HASWELL(dev_priv->dev)) in __gen6_gt_force_wake_get()
4293 __gen6_gt_wait_for_thread_c0(dev_priv); in __gen6_gt_force_wake_get()
4296 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) in __gen6_gt_force_wake_mt_reset() argument
4303 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) in __gen6_gt_force_wake_mt_get() argument
4307 if (IS_HASWELL(dev_priv->dev)) in __gen6_gt_force_wake_mt_get()
4324 __gen6_gt_wait_for_thread_c0(dev_priv); in __gen6_gt_force_wake_mt_get()
4333 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) in gen6_gt_force_wake_get() argument
4336 mtx_lock(&dev_priv->gt_lock); in gen6_gt_force_wake_get()
4337 if (dev_priv->forcewake_count++ == 0) in gen6_gt_force_wake_get()
4338 dev_priv->gt.force_wake_get(dev_priv); in gen6_gt_force_wake_get()
4339 mtx_unlock(&dev_priv->gt_lock); in gen6_gt_force_wake_get()
4342 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) in gen6_gt_check_fifodbg() argument
4351 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) in __gen6_gt_force_wake_put() argument
4356 gen6_gt_check_fifodbg(dev_priv); in __gen6_gt_force_wake_put()
4359 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) in __gen6_gt_force_wake_mt_put() argument
4364 gen6_gt_check_fifodbg(dev_priv); in __gen6_gt_force_wake_mt_put()
4370 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) in gen6_gt_force_wake_put() argument
4373 mtx_lock(&dev_priv->gt_lock); in gen6_gt_force_wake_put()
4374 if (--dev_priv->forcewake_count == 0) in gen6_gt_force_wake_put()
4375 dev_priv->gt.force_wake_put(dev_priv); in gen6_gt_force_wake_put()
4376 mtx_unlock(&dev_priv->gt_lock); in gen6_gt_force_wake_put()
4379 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) in __gen6_gt_wait_for_fifo() argument
4383 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { in __gen6_gt_wait_for_fifo()
4392 dev_priv->gt_fifo_count = fifo; in __gen6_gt_wait_for_fifo()
4394 dev_priv->gt_fifo_count--; in __gen6_gt_wait_for_fifo()
4399 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) in vlv_force_wake_reset() argument
4406 static void vlv_force_wake_get(struct drm_i915_private *dev_priv) in vlv_force_wake_get() argument
4418 __gen6_gt_wait_for_thread_c0(dev_priv); in vlv_force_wake_get()
4421 static void vlv_force_wake_put(struct drm_i915_private *dev_priv) in vlv_force_wake_put() argument
4426 gen6_gt_check_fifodbg(dev_priv); in vlv_force_wake_put()
4431 struct drm_i915_private *dev_priv = dev->dev_private; in intel_gt_reset() local
4434 vlv_force_wake_reset(dev_priv); in intel_gt_reset()
4436 __gen6_gt_force_wake_reset(dev_priv); in intel_gt_reset()
4438 __gen6_gt_force_wake_mt_reset(dev_priv); in intel_gt_reset()
4444 struct drm_i915_private *dev_priv = dev->dev_private; in intel_gt_init() local
4446 mtx_init(&dev_priv->gt_lock, "i915_gt_lock", NULL, MTX_DEF); in intel_gt_init()
4451 dev_priv->gt.force_wake_get = vlv_force_wake_get; in intel_gt_init()
4452 dev_priv->gt.force_wake_put = vlv_force_wake_put; in intel_gt_init()
4454 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; in intel_gt_init()
4455 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; in intel_gt_init()
4457 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; in intel_gt_init()
4458 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; in intel_gt_init()
4460 TIMEOUT_TASK_INIT(dev_priv->wq, &dev_priv->rps.delayed_resume_work, 0, in intel_gt_init()
4461 intel_gen6_powersave_work, dev_priv); in intel_gt_init()
4464 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) in sandybridge_pcode_read() argument
4466 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED); in sandybridge_pcode_read()
4488 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) in sandybridge_pcode_write() argument
4490 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED); in sandybridge_pcode_write()