48 static bool is_edp(struct intel_dp *intel_dp)  in is_edp()  argument
50 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in is_edp()
63 static bool is_pch_edp(struct intel_dp *intel_dp)  in is_pch_edp()  argument
65 	return intel_dp->is_pch_edp;  in is_pch_edp()
74 static bool is_cpu_edp(struct intel_dp *intel_dp)  in is_cpu_edp()  argument
76 	return is_edp(intel_dp) && !is_pch_edp(intel_dp);  in is_cpu_edp()
79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)  in intel_dp_to_dev()  argument
81 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in intel_dp_to_dev()
86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)  in intel_attached_dp()
100 	struct intel_dp *intel_dp;  in intel_encoder_is_pch_edp()  local
105 	intel_dp = enc_to_intel_dp(encoder);  in intel_encoder_is_pch_edp()
107 	return is_pch_edp(intel_dp);  in intel_encoder_is_pch_edp()
110 static void intel_dp_link_down(struct intel_dp *intel_dp);
116 	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);  in intel_edp_link_config()  local
118 	*lane_num = intel_dp->lane_count;  in intel_edp_link_config()
119 	*link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);  in intel_edp_link_config()
126 	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);  in intel_edp_target_clock()  local
127 	struct intel_connector *intel_connector = intel_dp->attached_connector;  in intel_edp_target_clock()
136 intel_dp_max_link_bw(struct intel_dp *intel_dp)  in intel_dp_max_link_bw()  argument
138 	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];  in intel_dp_max_link_bw()
190 intel_dp_adjust_dithering(struct intel_dp *intel_dp,  in intel_dp_adjust_dithering()  argument
194 	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));  in intel_dp_adjust_dithering()
195 	int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);  in intel_dp_adjust_dithering()
220 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_mode_valid()  local
224 	if (is_edp(intel_dp) && fixed_mode) {  in intel_dp_mode_valid()
232 	if (!intel_dp_adjust_dithering(intel_dp, mode, false))  in intel_dp_mode_valid()
301 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)  in ironlake_edp_have_panel_power()  argument
303 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_edp_have_panel_power()
309 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)  in ironlake_edp_have_panel_vdd()  argument
311 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_edp_have_panel_vdd()
318 intel_dp_check_edp(struct intel_dp *intel_dp)  in intel_dp_check_edp()  argument
320 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in intel_dp_check_edp()
323 	if (!is_edp(intel_dp))  in intel_dp_check_edp()
325 	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {  in intel_dp_check_edp()
334 intel_dp_aux_ch(struct intel_dp *intel_dp,  in intel_dp_aux_ch()  argument
338 	uint32_t output_reg = intel_dp->output_reg;  in intel_dp_aux_ch()
339 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in intel_dp_aux_ch()
373 	intel_dp_check_edp(intel_dp);  in intel_dp_aux_ch()
381 	if (is_cpu_edp(intel_dp)) {  in intel_dp_aux_ch()
487 intel_dp_aux_native_write(struct intel_dp *intel_dp,  in intel_dp_aux_native_write()  argument
495 	intel_dp_check_edp(intel_dp);  in intel_dp_aux_native_write()
505 		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);  in intel_dp_aux_native_write()
520 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,  in intel_dp_aux_native_write_1()  argument
523 	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);  in intel_dp_aux_native_write_1()
528 intel_dp_aux_native_read(struct intel_dp *intel_dp,  in intel_dp_aux_native_read()  argument
538 	intel_dp_check_edp(intel_dp);  in intel_dp_aux_native_read()
548 		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,  in intel_dp_aux_native_read()
571 	struct intel_dp *intel_dp = algo_data->priv;  in intel_dp_i2c_aux_ch()  local
580 	intel_dp_check_edp(intel_dp);  in intel_dp_i2c_aux_ch()
612 		ret = intel_dp_aux_ch(intel_dp,  in intel_dp_i2c_aux_ch()
662 intel_dp_i2c_init(struct intel_dp *intel_dp,  in intel_dp_i2c_init()  argument
669 	ironlake_edp_panel_vdd_on(intel_dp);  in intel_dp_i2c_init()
671 	    intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,  in intel_dp_i2c_init()
672 	    &intel_dp->adapter);  in intel_dp_i2c_init()
673 	ironlake_edp_panel_vdd_off(intel_dp, false);  in intel_dp_i2c_init()
683 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);  in intel_dp_mode_fixup()  local
684 	struct intel_connector *intel_connector = intel_dp->attached_connector;  in intel_dp_mode_fixup()
686 	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);  in intel_dp_mode_fixup()
687 	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;  in intel_dp_mode_fixup()
691 	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {  in intel_dp_mode_fixup()
706 	if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))  in intel_dp_mode_fixup()
717 				intel_dp->link_bw = bws[clock];  in intel_dp_mode_fixup()
718 				intel_dp->lane_count = lane_count;  in intel_dp_mode_fixup()
719 				adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);  in intel_dp_mode_fixup()
722 				       intel_dp->link_bw, intel_dp->lane_count,  in intel_dp_mode_fixup()
773 	struct intel_dp *intel_dp;  in intel_dp_set_m_n()  local
786 		intel_dp = enc_to_intel_dp(&intel_encoder->base);  in intel_dp_set_m_n()
791 			lane_count = intel_dp->lane_count;  in intel_dp_set_m_n()
838 void intel_dp_init_link_config(struct intel_dp *intel_dp)  in intel_dp_init_link_config()  argument
840 	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);  in intel_dp_init_link_config()
841 	intel_dp->link_configuration[0] = intel_dp->link_bw;  in intel_dp_init_link_config()
842 	intel_dp->link_configuration[1] = intel_dp->lane_count;  in intel_dp_init_link_config()
843 	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;  in intel_dp_init_link_config()
847 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&  in intel_dp_init_link_config()
848 	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {  in intel_dp_init_link_config()
849 		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;  in intel_dp_init_link_config()
859 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);  in intel_dp_mode_set()  local
883 	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;  in intel_dp_mode_set()
886 	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;  in intel_dp_mode_set()
888 	switch (intel_dp->lane_count) {  in intel_dp_mode_set()
890 		intel_dp->DP |= DP_PORT_WIDTH_1;  in intel_dp_mode_set()
893 		intel_dp->DP |= DP_PORT_WIDTH_2;  in intel_dp_mode_set()
896 		intel_dp->DP |= DP_PORT_WIDTH_4;  in intel_dp_mode_set()
899 	if (intel_dp->has_audio) {  in intel_dp_mode_set()
902 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;  in intel_dp_mode_set()
906 	intel_dp_init_link_config(intel_dp);  in intel_dp_mode_set()
910 	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {  in intel_dp_mode_set()
912 			intel_dp->DP |= DP_SYNC_HS_HIGH;  in intel_dp_mode_set()
914 			intel_dp->DP |= DP_SYNC_VS_HIGH;  in intel_dp_mode_set()
915 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;  in intel_dp_mode_set()
917 		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)  in intel_dp_mode_set()
918 			intel_dp->DP |= DP_ENHANCED_FRAMING;  in intel_dp_mode_set()
920 		intel_dp->DP |= intel_crtc->pipe << 29;  in intel_dp_mode_set()
924 			intel_dp->DP |= DP_PLL_FREQ_160MHZ;  in intel_dp_mode_set()
926 			intel_dp->DP |= DP_PLL_FREQ_270MHZ;  in intel_dp_mode_set()
927 	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {  in intel_dp_mode_set()
928 		intel_dp->DP |= intel_dp->color_range;  in intel_dp_mode_set()
931 			intel_dp->DP |= DP_SYNC_HS_HIGH;  in intel_dp_mode_set()
933 			intel_dp->DP |= DP_SYNC_VS_HIGH;  in intel_dp_mode_set()
934 		intel_dp->DP |= DP_LINK_TRAIN_OFF;  in intel_dp_mode_set()
936 		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)  in intel_dp_mode_set()
937 			intel_dp->DP |= DP_ENHANCED_FRAMING;  in intel_dp_mode_set()
940 			intel_dp->DP |= DP_PIPEB_SELECT;  in intel_dp_mode_set()
942 		if (is_cpu_edp(intel_dp)) {  in intel_dp_mode_set()
945 				intel_dp->DP |= DP_PLL_FREQ_160MHZ;  in intel_dp_mode_set()
947 				intel_dp->DP |= DP_PLL_FREQ_270MHZ;  in intel_dp_mode_set()
950 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;  in intel_dp_mode_set()
963 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,  in ironlake_wait_panel_status()  argument
967 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_wait_panel_status()
982 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)  in ironlake_wait_panel_on()  argument
985 	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);  in ironlake_wait_panel_on()
988 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)  in ironlake_wait_panel_off()  argument
991 	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);  in ironlake_wait_panel_off()
994 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)  in ironlake_wait_panel_power_cycle()  argument
997 	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);  in ironlake_wait_panel_power_cycle()
1014 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)  in ironlake_edp_panel_vdd_on()  argument
1016 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_edp_panel_vdd_on()
1020 	if (!is_edp(intel_dp))  in ironlake_edp_panel_vdd_on()
1024 	WARN(intel_dp->want_panel_vdd,  in ironlake_edp_panel_vdd_on()
1027 	intel_dp->want_panel_vdd = true;  in ironlake_edp_panel_vdd_on()
1029 	if (ironlake_edp_have_panel_vdd(intel_dp)) {  in ironlake_edp_panel_vdd_on()
1034 	if (!ironlake_edp_have_panel_power(intel_dp))  in ironlake_edp_panel_vdd_on()
1035 		ironlake_wait_panel_power_cycle(intel_dp);  in ironlake_edp_panel_vdd_on()
1047 	if (!ironlake_edp_have_panel_power(intel_dp)) {  in ironlake_edp_panel_vdd_on()
1049 		DRM_MSLEEP(intel_dp->panel_power_up_delay);  in ironlake_edp_panel_vdd_on()
1053 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)  in ironlake_panel_vdd_off_sync()  argument
1055 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_panel_vdd_off_sync()
1059 	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {  in ironlake_panel_vdd_off_sync()
1069 		DRM_MSLEEP(intel_dp->panel_power_down_delay);  in ironlake_panel_vdd_off_sync()
1075 	struct intel_dp *intel_dp = arg;  in ironlake_panel_vdd_work()  local
1076 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_panel_vdd_work()
1079 	ironlake_panel_vdd_off_sync(intel_dp);  in ironlake_panel_vdd_work()
1083 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)  in ironlake_edp_panel_vdd_off()  argument
1085 	if (!is_edp(intel_dp))  in ironlake_edp_panel_vdd_off()
1088 	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);  in ironlake_edp_panel_vdd_off()
1089 	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");  in ironlake_edp_panel_vdd_off()
1091 	intel_dp->want_panel_vdd = false;  in ironlake_edp_panel_vdd_off()
1094 		ironlake_panel_vdd_off_sync(intel_dp);  in ironlake_edp_panel_vdd_off()
1101 		struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in ironlake_edp_panel_vdd_off()
1105 		    &intel_dp->panel_vdd_work,  in ironlake_edp_panel_vdd_off()
1106 		    msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));  in ironlake_edp_panel_vdd_off()
1110 void ironlake_edp_panel_on(struct intel_dp *intel_dp)  in ironlake_edp_panel_on()  argument
1112 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_edp_panel_on()
1116 	if (!is_edp(intel_dp))  in ironlake_edp_panel_on()
1121 	if (ironlake_edp_have_panel_power(intel_dp)) {  in ironlake_edp_panel_on()
1126 	ironlake_wait_panel_power_cycle(intel_dp);  in ironlake_edp_panel_on()
1143 	ironlake_wait_panel_on(intel_dp);  in ironlake_edp_panel_on()
1152 void ironlake_edp_panel_off(struct intel_dp *intel_dp)  in ironlake_edp_panel_off()  argument
1154 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_edp_panel_off()
1158 	if (!is_edp(intel_dp))  in ironlake_edp_panel_off()
1163 	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");  in ironlake_edp_panel_off()
1172 	intel_dp->want_panel_vdd = false;  in ironlake_edp_panel_off()
1174 	ironlake_wait_panel_off(intel_dp);  in ironlake_edp_panel_off()
1177 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)  in ironlake_edp_backlight_on()  argument
1179 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in ironlake_edp_backlight_on()
1185 	if (!is_edp(intel_dp))  in ironlake_edp_backlight_on()
1195 	DRM_MSLEEP(intel_dp->backlight_on_delay);  in ironlake_edp_backlight_on()
1204 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)  in ironlake_edp_backlight_off()  argument
1206 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_edp_backlight_off()
1210 	if (!is_edp(intel_dp))  in ironlake_edp_backlight_off()
1220 	DRM_MSLEEP(intel_dp->backlight_off_delay);  in ironlake_edp_backlight_off()
1223 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)  in ironlake_edp_pll_on()  argument
1225 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in ironlake_edp_pll_on()
1242 	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);  in ironlake_edp_pll_on()
1243 	intel_dp->DP |= DP_PLL_ENABLE;  in ironlake_edp_pll_on()
1244 	I915_WRITE(DP_A, intel_dp->DP);  in ironlake_edp_pll_on()
1249 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)  in ironlake_edp_pll_off()  argument
1251 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in ironlake_edp_pll_off()
1275 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)  in intel_dp_sink_dpms()  argument
1280 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_sink_dpms()
1284 		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,  in intel_dp_sink_dpms()
1294 			ret = intel_dp_aux_native_write_1(intel_dp,  in intel_dp_sink_dpms()
1307 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);  in intel_dp_get_hw_state()  local
1310 	u32 tmp = I915_READ(intel_dp->output_reg);  in intel_dp_get_hw_state()
1315 	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {  in intel_dp_get_hw_state()
1317 	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {  in intel_dp_get_hw_state()
1324 		switch (intel_dp->output_reg) {  in intel_dp_get_hw_state()
1347 			      intel_dp->output_reg);  in intel_dp_get_hw_state()
1355 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);  in intel_disable_dp()  local
1359 	ironlake_edp_panel_vdd_on(intel_dp);  in intel_disable_dp()
1360 	ironlake_edp_backlight_off(intel_dp);  in intel_disable_dp()
1361 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);  in intel_disable_dp()
1362 	ironlake_edp_panel_off(intel_dp);  in intel_disable_dp()
1365 	if (!is_cpu_edp(intel_dp))  in intel_disable_dp()
1366 		intel_dp_link_down(intel_dp);  in intel_disable_dp()
1371 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);  in intel_post_disable_dp()  local
1373 	if (is_cpu_edp(intel_dp)) {  in intel_post_disable_dp()
1374 		intel_dp_link_down(intel_dp);  in intel_post_disable_dp()
1375 		ironlake_edp_pll_off(intel_dp);  in intel_post_disable_dp()
1381 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);  in intel_enable_dp()  local
1384 	uint32_t dp_reg = I915_READ(intel_dp->output_reg);  in intel_enable_dp()
1389 	ironlake_edp_panel_vdd_on(intel_dp);  in intel_enable_dp()
1390 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);  in intel_enable_dp()
1391 	intel_dp_start_link_train(intel_dp);  in intel_enable_dp()
1392 	ironlake_edp_panel_on(intel_dp);  in intel_enable_dp()
1393 	ironlake_edp_panel_vdd_off(intel_dp, true);  in intel_enable_dp()
1394 	intel_dp_complete_link_train(intel_dp);  in intel_enable_dp()
1395 	ironlake_edp_backlight_on(intel_dp);  in intel_enable_dp()
1400 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);  in intel_pre_enable_dp()  local
1402 	if (is_cpu_edp(intel_dp))  in intel_pre_enable_dp()
1403 		ironlake_edp_pll_on(intel_dp);  in intel_pre_enable_dp()
1411 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,  in intel_dp_aux_native_read_retry()  argument
1421 		ret = intel_dp_aux_native_read(intel_dp, address, recv,  in intel_dp_aux_native_read_retry()
1436 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])  in intel_dp_get_link_status()  argument
1438 	return intel_dp_aux_native_read_retry(intel_dp,  in intel_dp_get_link_status()
1462 intel_dp_voltage_max(struct intel_dp *intel_dp)  in intel_dp_voltage_max()  argument
1464 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in intel_dp_voltage_max()
1466 	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))  in intel_dp_voltage_max()
1468 	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))  in intel_dp_voltage_max()
1475 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)  in intel_dp_pre_emphasis_max()  argument
1477 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in intel_dp_pre_emphasis_max()
1491 	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {  in intel_dp_pre_emphasis_max()
1517 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])  in intel_get_adjust_train()  argument
1525 	for (lane = 0; lane < intel_dp->lane_count; lane++) {  in intel_get_adjust_train()
1535 	voltage_max = intel_dp_voltage_max(intel_dp);  in intel_get_adjust_train()
1539 	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);  in intel_get_adjust_train()
1544 		intel_dp->train_set[lane] = v | p;  in intel_get_adjust_train()
1679 intel_dp_set_link_train(struct intel_dp *intel_dp,  in intel_dp_set_link_train()  argument
1683 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in intel_dp_set_link_train()
1729 		   (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {  in intel_dp_set_link_train()
1768 	I915_WRITE(intel_dp->output_reg, dp_reg_value);  in intel_dp_set_link_train()
1769 	POSTING_READ(intel_dp->output_reg);  in intel_dp_set_link_train()
1771 	intel_dp_aux_native_write_1(intel_dp,  in intel_dp_set_link_train()
1777 		ret = intel_dp_aux_native_write(intel_dp,  in intel_dp_set_link_train()
1779 						intel_dp->train_set,  in intel_dp_set_link_train()
1780 						intel_dp->lane_count);  in intel_dp_set_link_train()
1781 		if (ret != intel_dp->lane_count)  in intel_dp_set_link_train()
1790 intel_dp_start_link_train(struct intel_dp *intel_dp)  in intel_dp_start_link_train()  argument
1792 	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;  in intel_dp_start_link_train()
1798 	uint32_t DP = intel_dp->DP;  in intel_dp_start_link_train()
1804 	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,  in intel_dp_start_link_train()
1805 				  intel_dp->link_configuration,  in intel_dp_start_link_train()
1810 	memset(intel_dp->train_set, 0, 4);  in intel_dp_start_link_train()
1822 							intel_dp->train_set[0]);  in intel_dp_start_link_train()
1824 		} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {  in intel_dp_start_link_train()
1825 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);  in intel_dp_start_link_train()
1827 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {  in intel_dp_start_link_train()
1828 			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);  in intel_dp_start_link_train()
1831 			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);  in intel_dp_start_link_train()
1838 		if (!intel_dp_set_link_train(intel_dp, DP,  in intel_dp_start_link_train()
1843 		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);  in intel_dp_start_link_train()
1844 		if (!intel_dp_get_link_status(intel_dp, link_status)) {  in intel_dp_start_link_train()
1849 		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {  in intel_dp_start_link_train()
1856 		for (i = 0; i < intel_dp->lane_count; i++)  in intel_dp_start_link_train()
1857 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in intel_dp_start_link_train()
1859 		if (i == intel_dp->lane_count) {  in intel_dp_start_link_train()
1865 			memset(intel_dp->train_set, 0, 4);  in intel_dp_start_link_train()
1871 		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in intel_dp_start_link_train()
1879 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in intel_dp_start_link_train()
1882 		intel_get_adjust_train(intel_dp, link_status);  in intel_dp_start_link_train()
1885 	intel_dp->DP = DP;  in intel_dp_start_link_train()
1889 intel_dp_complete_link_train(struct intel_dp *intel_dp)  in intel_dp_complete_link_train()  argument
1891 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in intel_dp_complete_link_train()
1894 	uint32_t DP = intel_dp->DP;  in intel_dp_complete_link_train()
1907 			intel_dp_link_down(intel_dp);  in intel_dp_complete_link_train()
1912 			signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);  in intel_dp_complete_link_train()
1914 		} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {  in intel_dp_complete_link_train()
1915 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);  in intel_dp_complete_link_train()
1917 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {  in intel_dp_complete_link_train()
1918 			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);  in intel_dp_complete_link_train()
1921 			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);  in intel_dp_complete_link_train()
1926 		if (!intel_dp_set_link_train(intel_dp, DP,  in intel_dp_complete_link_train()
1931 		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);  in intel_dp_complete_link_train()
1932 		if (!intel_dp_get_link_status(intel_dp, link_status))  in intel_dp_complete_link_train()
1936 		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {  in intel_dp_complete_link_train()
1937 			intel_dp_start_link_train(intel_dp);  in intel_dp_complete_link_train()
1942 		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {  in intel_dp_complete_link_train()
1949 			intel_dp_link_down(intel_dp);  in intel_dp_complete_link_train()
1950 			intel_dp_start_link_train(intel_dp);  in intel_dp_complete_link_train()
1957 		intel_get_adjust_train(intel_dp, link_status);  in intel_dp_complete_link_train()
1964 	intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);  in intel_dp_complete_link_train()
1968 intel_dp_link_down(struct intel_dp *intel_dp)  in intel_dp_link_down()  argument
1970 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in intel_dp_link_down()
1973 	uint32_t DP = intel_dp->DP;  in intel_dp_link_down()
1993 	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))  in intel_dp_link_down()
1998 	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {  in intel_dp_link_down()
2000 		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);  in intel_dp_link_down()
2003 		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in intel_dp_link_down()
2005 	POSTING_READ(intel_dp->output_reg);  in intel_dp_link_down()
2010 	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {  in intel_dp_link_down()
2022 		I915_WRITE(intel_dp->output_reg, DP);  in intel_dp_link_down()
2036 			POSTING_READ(intel_dp->output_reg);  in intel_dp_link_down()
2043 	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in intel_dp_link_down()
2044 	POSTING_READ(intel_dp->output_reg);  in intel_dp_link_down()
2045 	DRM_MSLEEP(intel_dp->panel_power_down_delay);  in intel_dp_link_down()
2049 intel_dp_get_dpcd(struct intel_dp *intel_dp)  in intel_dp_get_dpcd()  argument
2051 	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,  in intel_dp_get_dpcd()
2052 					   sizeof(intel_dp->dpcd)) == 0)  in intel_dp_get_dpcd()
2055 	if (intel_dp->dpcd[DP_DPCD_REV] == 0)  in intel_dp_get_dpcd()
2058 	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in intel_dp_get_dpcd()
2062 	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)  in intel_dp_get_dpcd()
2065 	if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,  in intel_dp_get_dpcd()
2066 					   intel_dp->downstream_ports,  in intel_dp_get_dpcd()
2074 intel_dp_probe_oui(struct intel_dp *intel_dp)  in intel_dp_probe_oui()  argument
2078 	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))  in intel_dp_probe_oui()
2081 	ironlake_edp_panel_vdd_on(intel_dp);  in intel_dp_probe_oui()
2083 	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))  in intel_dp_probe_oui()
2087 	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))  in intel_dp_probe_oui()
2091 	ironlake_edp_panel_vdd_off(intel_dp, false);  in intel_dp_probe_oui()
2095 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)  in intel_dp_get_sink_irq()  argument
2099 	ret = intel_dp_aux_native_read_retry(intel_dp,  in intel_dp_get_sink_irq()
2109 intel_dp_handle_test_request(struct intel_dp *intel_dp)  in intel_dp_handle_test_request()  argument
2112 	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);  in intel_dp_handle_test_request()
2125 intel_dp_check_link_status(struct intel_dp *intel_dp)  in intel_dp_check_link_status()  argument
2127 	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_check_link_status()
2138 	if (!intel_dp_get_link_status(intel_dp, link_status)) {  in intel_dp_check_link_status()
2139 		intel_dp_link_down(intel_dp);  in intel_dp_check_link_status()
2144 	if (!intel_dp_get_dpcd(intel_dp)) {  in intel_dp_check_link_status()
2145 		intel_dp_link_down(intel_dp);  in intel_dp_check_link_status()
2150 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&  in intel_dp_check_link_status()
2151 	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {  in intel_dp_check_link_status()
2153 		intel_dp_aux_native_write_1(intel_dp,  in intel_dp_check_link_status()
2158 			intel_dp_handle_test_request(intel_dp);  in intel_dp_check_link_status()
2163 	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {  in intel_dp_check_link_status()
2166 		intel_dp_start_link_train(intel_dp);  in intel_dp_check_link_status()
2167 		intel_dp_complete_link_train(intel_dp);  in intel_dp_check_link_status()
2173 intel_dp_detect_dpcd(struct intel_dp *intel_dp)  in intel_dp_detect_dpcd()  argument
2175 	uint8_t *dpcd = intel_dp->dpcd;  in intel_dp_detect_dpcd()
2179 	if (!intel_dp_get_dpcd(intel_dp))  in intel_dp_detect_dpcd()
2187 	hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);  in intel_dp_detect_dpcd()
2190 		if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,  in intel_dp_detect_dpcd()
2198 	if (drm_probe_ddc(intel_dp->adapter))  in intel_dp_detect_dpcd()
2202 	type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;  in intel_dp_detect_dpcd()
2212 ironlake_dp_detect(struct intel_dp *intel_dp)  in ironlake_dp_detect()  argument
2214 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in ironlake_dp_detect()
2218 	if (is_edp(intel_dp)) {  in ironlake_dp_detect()
2225 	return intel_dp_detect_dpcd(intel_dp);  in ironlake_dp_detect()
2229 g4x_dp_detect(struct intel_dp *intel_dp)  in g4x_dp_detect()  argument
2231 	struct drm_device *dev = intel_dp_to_dev(intel_dp);  in g4x_dp_detect()
2235 	switch (intel_dp->output_reg) {  in g4x_dp_detect()
2252 	return intel_dp_detect_dpcd(intel_dp);  in g4x_dp_detect()
2309 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_detect()  local
2310 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);  in intel_dp_detect()
2315 	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];  in intel_dp_detect()
2317 	intel_dp->has_audio = false;  in intel_dp_detect()
2320 		status = ironlake_dp_detect(intel_dp);  in intel_dp_detect()
2322 		status = g4x_dp_detect(intel_dp);  in intel_dp_detect()
2324 	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),  in intel_dp_detect()
2331 	intel_dp_probe_oui(intel_dp);  in intel_dp_detect()
2333 	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {  in intel_dp_detect()
2334 		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);  in intel_dp_detect()
2336 		edid = intel_dp_get_edid(connector, intel_dp->adapter);  in intel_dp_detect()
2338 			intel_dp->has_audio = drm_detect_monitor_audio(edid);  in intel_dp_detect()
2350 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_get_modes()  local
2358 	ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);  in intel_dp_get_modes()
2363 	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {  in intel_dp_get_modes()
2378 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_detect_audio()  local
2382 	edid = intel_dp_get_edid(connector, intel_dp->adapter);  in intel_dp_detect_audio()
2399 	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);  in intel_dp_set_property()  local
2410 		if (i == intel_dp->force_audio)  in intel_dp_set_property()
2413 		intel_dp->force_audio = i;  in intel_dp_set_property()
2420 		if (has_audio == intel_dp->has_audio)  in intel_dp_set_property()
2423 		intel_dp->has_audio = has_audio;  in intel_dp_set_property()
2428 		if (val == !!intel_dp->color_range)  in intel_dp_set_property()
2431 		intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;  in intel_dp_set_property()
2435 	if (is_edp(intel_dp) &&  in intel_dp_set_property()
2466 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_destroy()  local
2471 	if (is_edp(intel_dp))  in intel_dp_destroy()
2481 	struct intel_dp *intel_dp = &intel_dig_port->dp;  in intel_dp_encoder_destroy()  local
2484 	if (intel_dp->dp_iic_bus != NULL) {  in intel_dp_encoder_destroy()
2485 		if (intel_dp->adapter != NULL) {  in intel_dp_encoder_destroy()
2486 			device_delete_child(intel_dp->dp_iic_bus,  in intel_dp_encoder_destroy()
2487 			    intel_dp->adapter);  in intel_dp_encoder_destroy()
2489 		device_delete_child(dev->dev, intel_dp->dp_iic_bus);  in intel_dp_encoder_destroy()
2492 	if (is_edp(intel_dp)) {  in intel_dp_encoder_destroy()
2496 		    &intel_dp->panel_vdd_work, NULL);  in intel_dp_encoder_destroy()
2498 		    &intel_dp->panel_vdd_work);  in intel_dp_encoder_destroy()
2499 		ironlake_panel_vdd_off_sync(intel_dp);  in intel_dp_encoder_destroy()
2531 	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);  in intel_dp_hot_plug()  local
2533 	intel_dp_check_link_status(intel_dp);  in intel_dp_hot_plug()
2542 	struct intel_dp *intel_dp;  in intel_trans_dp_port_sel()  local
2545 		intel_dp = enc_to_intel_dp(&intel_encoder->base);  in intel_trans_dp_port_sel()
2549 			return intel_dp->output_reg;  in intel_trans_dp_port_sel()
2576 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)  in intel_dp_add_properties()  argument
2583 	if (is_edp(intel_dp)) {  in intel_dp_add_properties()
2595 				    struct intel_dp *intel_dp,  in intel_dp_init_panel_power_sequencer()  argument
2660 	intel_dp->panel_power_up_delay = get_delay(t1_t3);  in intel_dp_init_panel_power_sequencer()
2661 	intel_dp->backlight_on_delay = get_delay(t8);  in intel_dp_init_panel_power_sequencer()
2662 	intel_dp->backlight_off_delay = get_delay(t9);  in intel_dp_init_panel_power_sequencer()
2663 	intel_dp->panel_power_down_delay = get_delay(t10);  in intel_dp_init_panel_power_sequencer()
2664 	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);  in intel_dp_init_panel_power_sequencer()
2668 		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,  in intel_dp_init_panel_power_sequencer()
2669 		      intel_dp->panel_power_cycle_delay);  in intel_dp_init_panel_power_sequencer()
2672 		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);  in intel_dp_init_panel_power_sequencer()
2680 					      struct intel_dp *intel_dp,  in intel_dp_init_panel_power_sequencer_registers()  argument
2701 		if (is_cpu_edp(intel_dp))  in intel_dp_init_panel_power_sequencer_registers()
2722 	struct intel_dp *intel_dp = &intel_dig_port->dp;  in intel_dp_init_connector()  local
2733 	intel_dp->DP = I915_READ(intel_dp->output_reg);  in intel_dp_init_connector()
2734 	intel_dp->attached_connector = intel_connector;  in intel_dp_init_connector()
2738 			intel_dp->is_pch_edp = true;  in intel_dp_init_connector()
2747 	} else if (port == PORT_A || is_pch_edp(intel_dp)) {  in intel_dp_init_connector()
2765 	TIMEOUT_TASK_INIT(dev_priv->wq, &intel_dp->panel_vdd_work, 0,  in intel_dp_init_connector()
2766 	    ironlake_panel_vdd_work, intel_dp);  in intel_dp_init_connector()
2798 	if (is_edp(intel_dp))  in intel_dp_init_connector()
2799 		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);  in intel_dp_init_connector()
2801 	intel_dp_i2c_init(intel_dp, intel_connector, name);  in intel_dp_init_connector()
2804 	if (is_edp(intel_dp)) {  in intel_dp_init_connector()
2810 		ironlake_edp_panel_vdd_on(intel_dp);  in intel_dp_init_connector()
2811 		ret = intel_dp_get_dpcd(intel_dp);  in intel_dp_init_connector()
2812 		ironlake_edp_panel_vdd_off(intel_dp, false);  in intel_dp_init_connector()
2815 			if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)  in intel_dp_init_connector()
2817 					intel_dp->dpcd[DP_MAX_DOWNSPREAD] &  in intel_dp_init_connector()
2828 		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,  in intel_dp_init_connector()
2831 		ironlake_edp_panel_vdd_on(intel_dp);  in intel_dp_init_connector()
2832 		edid = drm_get_edid(connector, intel_dp->adapter);  in intel_dp_init_connector()
2864 		ironlake_edp_panel_vdd_off(intel_dp, false);  in intel_dp_init_connector()
2867 	if (is_edp(intel_dp)) {  in intel_dp_init_connector()
2872 	intel_dp_add_properties(intel_dp, connector);  in intel_dp_init_connector()