Lines Matching refs:pipe
931 enum pipe pipe) in intel_pipe_to_cpu_transcoder() argument
933 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_pipe_to_cpu_transcoder()
939 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) in ironlake_wait_for_vblank() argument
942 u32 frame, frame_reg = PIPEFRAME(pipe); in ironlake_wait_for_vblank()
958 void intel_wait_for_vblank(struct drm_device *dev, int pipe) in intel_wait_for_vblank() argument
961 int pipestat_reg = PIPESTAT(pipe); in intel_wait_for_vblank()
964 ironlake_wait_for_vblank(dev, pipe); in intel_wait_for_vblank()
1008 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) in intel_wait_for_pipe_off() argument
1012 pipe); in intel_wait_for_pipe_off()
1023 int reg = PIPEDSL(pipe); in intel_wait_for_pipe_off()
1049 enum pipe pipe, bool state) in assert_pll() argument
1055 reg = DPLL(pipe); in assert_pll()
1095 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, in assert_pch_pll()
1097 cur_state, crtc->pipe, pch_dpll)) { in assert_pch_pll()
1098 cur_state = !!(val >> (4*crtc->pipe + 3)); in assert_pch_pll()
1103 crtc->pipe, in assert_pch_pll()
1112 enum pipe pipe, bool state) in assert_fdi_tx() argument
1118 pipe); in assert_fdi_tx()
1126 reg = FDI_TX_CTL(pipe); in assert_fdi_tx()
1138 enum pipe pipe, bool state) in assert_fdi_rx() argument
1144 reg = FDI_RX_CTL(pipe); in assert_fdi_rx()
1155 enum pipe pipe) in assert_fdi_tx_pll_enabled() argument
1168 reg = FDI_TX_CTL(pipe); in assert_fdi_tx_pll_enabled()
1174 enum pipe pipe) in assert_fdi_rx_pll_enabled() argument
1179 reg = FDI_RX_CTL(pipe); in assert_fdi_rx_pll_enabled()
1185 enum pipe pipe) in assert_panel_unlocked() argument
1189 enum pipe panel_pipe = PIPE_A; in assert_panel_unlocked()
1208 WARN(panel_pipe == pipe && locked, in assert_panel_unlocked()
1210 pipe_name(pipe)); in assert_panel_unlocked()
1214 enum pipe pipe, bool state) in assert_pipe() argument
1220 pipe); in assert_pipe()
1223 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) in assert_pipe()
1231 pipe_name(pipe), state_string(state), state_string(cur_state)); in assert_pipe()
1253 enum pipe pipe) in assert_planes_disabled() argument
1261 reg = DSPCNTR(pipe); in assert_planes_disabled()
1265 plane_name(pipe)); in assert_planes_disabled()
1275 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, in assert_planes_disabled()
1277 plane_name(i), pipe_name(pipe)); in assert_planes_disabled()
1298 enum pipe pipe) in assert_transcoder_disabled() argument
1304 reg = TRANSCONF(pipe); in assert_transcoder_disabled()
1309 pipe_name(pipe)); in assert_transcoder_disabled()
1313 enum pipe pipe, u32 port_sel, u32 val) in dp_pipe_enabled() argument
1319 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); in dp_pipe_enabled()
1324 if ((val & DP_PIPE_MASK) != (pipe << 30)) in dp_pipe_enabled()
1331 enum pipe pipe, u32 val) in hdmi_pipe_enabled() argument
1337 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) in hdmi_pipe_enabled()
1340 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) in hdmi_pipe_enabled()
1347 enum pipe pipe, u32 val) in lvds_pipe_enabled() argument
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) in lvds_pipe_enabled()
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) in lvds_pipe_enabled()
1363 enum pipe pipe, u32 val) in adpa_pipe_enabled() argument
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) in adpa_pipe_enabled()
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) in adpa_pipe_enabled()
1378 enum pipe pipe, int reg, u32 port_sel) in assert_pch_dp_disabled() argument
1381 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), in assert_pch_dp_disabled()
1383 reg, pipe_name(pipe)); in assert_pch_dp_disabled()
1391 enum pipe pipe, int reg) in assert_pch_hdmi_disabled() argument
1394 WARN(hdmi_pipe_enabled(dev_priv, pipe, val), in assert_pch_hdmi_disabled()
1396 reg, pipe_name(pipe)); in assert_pch_hdmi_disabled()
1404 enum pipe pipe) in assert_pch_ports_disabled() argument
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); in assert_pch_ports_disabled()
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); in assert_pch_ports_disabled()
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); in assert_pch_ports_disabled()
1415 WARN(adpa_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1417 pipe_name(pipe)); in assert_pch_ports_disabled()
1421 WARN(lvds_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1423 pipe_name(pipe)); in assert_pch_ports_disabled()
1425 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); in assert_pch_ports_disabled()
1426 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); in assert_pch_ports_disabled()
1427 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); in assert_pch_ports_disabled()
1443 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_enable_pll() argument
1453 assert_panel_unlocked(dev_priv, pipe); in intel_enable_pll()
1455 reg = DPLL(pipe); in intel_enable_pll()
1480 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_disable_pll() argument
1486 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) in intel_disable_pll()
1490 assert_pipe_disabled(dev_priv, pipe); in intel_disable_pll()
1492 reg = DPLL(pipe); in intel_disable_pll()
1644 assert_transcoder_disabled(dev_priv, intel_crtc->pipe); in intel_disable_pch_pll()
1657 enum pipe pipe) in ironlake_enable_pch_transcoder() argument
1660 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in ironlake_enable_pch_transcoder()
1672 assert_fdi_tx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1673 assert_fdi_rx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1678 reg = TRANS_CHICKEN2(pipe); in ironlake_enable_pch_transcoder()
1684 reg = TRANSCONF(pipe); in ironlake_enable_pch_transcoder()
1686 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
1709 DRM_ERROR("failed to enable transcoder %d\n", pipe); in ironlake_enable_pch_transcoder()
1721 assert_fdi_tx_enabled(dev_priv, (enum pipe)cpu_transcoder); in lpt_enable_pch_transcoder()
1722 assert_fdi_rx_enabled(dev_priv, (enum pipe)TRANSCODER_A); in lpt_enable_pch_transcoder()
1744 enum pipe pipe) in ironlake_disable_pch_transcoder() argument
1750 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
1751 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
1754 assert_pch_ports_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
1756 reg = TRANSCONF(pipe); in ironlake_disable_pch_transcoder()
1762 DRM_ERROR("failed to disable transcoder %d\n", pipe); in ironlake_disable_pch_transcoder()
1766 reg = TRANS_CHICKEN2(pipe); in ironlake_disable_pch_transcoder()
1804 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, in intel_enable_pipe() argument
1808 pipe); in intel_enable_pipe()
1816 pch_transcoder = (enum transcoder)pipe; in intel_enable_pipe()
1824 assert_pll_enabled(dev_priv, pipe); in intel_enable_pipe()
1828 assert_fdi_rx_pll_enabled(dev_priv, (enum pipe)pch_transcoder); in intel_enable_pipe()
1829 assert_fdi_tx_pll_enabled(dev_priv, (enum pipe)cpu_transcoder); in intel_enable_pipe()
1840 intel_wait_for_vblank(dev_priv->dev, pipe); in intel_enable_pipe()
1856 enum pipe pipe) in intel_disable_pipe() argument
1859 pipe); in intel_disable_pipe()
1867 assert_planes_disabled(dev_priv, pipe); in intel_disable_pipe()
1870 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) in intel_disable_pipe()
1879 intel_wait_for_pipe_off(dev_priv->dev, pipe); in intel_disable_pipe()
1904 enum plane plane, enum pipe pipe) in intel_enable_plane() argument
1910 assert_pipe_enabled(dev_priv, pipe); in intel_enable_plane()
1919 intel_wait_for_vblank(dev_priv->dev, pipe); in intel_enable_plane()
1931 enum plane plane, enum pipe pipe) in intel_disable_plane() argument
1943 intel_wait_for_vblank(dev_priv->dev, pipe); in intel_disable_plane()
2283 switch (intel_crtc->pipe) { in intel_crtc_update_sarea_pos()
2347 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_pipe_set_base()
2401 int pipe = intel_crtc->pipe; in intel_fdi_normal_train() local
2405 reg = FDI_TX_CTL(pipe); in intel_fdi_normal_train()
2416 reg = FDI_RX_CTL(pipe); in intel_fdi_normal_train()
2466 int pipe = intel_crtc->pipe; in ironlake_fdi_link_train() local
2471 assert_pipe_enabled(dev_priv, pipe); in ironlake_fdi_link_train()
2476 reg = FDI_RX_IMR(pipe); in ironlake_fdi_link_train()
2485 reg = FDI_TX_CTL(pipe); in ironlake_fdi_link_train()
2493 reg = FDI_RX_CTL(pipe); in ironlake_fdi_link_train()
2503 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); in ironlake_fdi_link_train()
2504 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | in ironlake_fdi_link_train()
2507 reg = FDI_RX_IIR(pipe); in ironlake_fdi_link_train()
2522 reg = FDI_TX_CTL(pipe); in ironlake_fdi_link_train()
2528 reg = FDI_RX_CTL(pipe); in ironlake_fdi_link_train()
2537 reg = FDI_RX_IIR(pipe); in ironlake_fdi_link_train()
2568 int pipe = intel_crtc->pipe; in gen6_fdi_link_train() local
2573 reg = FDI_RX_IMR(pipe); in gen6_fdi_link_train()
2583 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
2594 I915_WRITE(FDI_RX_MISC(pipe), in gen6_fdi_link_train()
2597 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
2612 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
2622 reg = FDI_RX_IIR(pipe); in gen6_fdi_link_train()
2639 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
2650 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
2665 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
2675 reg = FDI_RX_IIR(pipe); in gen6_fdi_link_train()
2700 int pipe = intel_crtc->pipe; in ivb_manual_fdi_link_train() local
2705 reg = FDI_RX_IMR(pipe); in ivb_manual_fdi_link_train()
2715 I915_READ(FDI_RX_IIR(pipe))); in ivb_manual_fdi_link_train()
2718 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
2729 I915_WRITE(FDI_RX_MISC(pipe), in ivb_manual_fdi_link_train()
2732 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
2744 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
2753 reg = FDI_RX_IIR(pipe); in ivb_manual_fdi_link_train()
2768 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
2776 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
2786 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
2795 reg = FDI_RX_IIR(pipe); in ivb_manual_fdi_link_train()
2815 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_enable() local
2820 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_enable()
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
2841 reg = FDI_TX_CTL(pipe); in ironlake_fdi_pll_enable()
2856 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_disable() local
2860 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_disable()
2865 reg = FDI_TX_CTL(pipe); in ironlake_fdi_pll_disable()
2872 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_disable()
2886 int pipe = intel_crtc->pipe; in ironlake_fdi_disable() local
2890 reg = FDI_TX_CTL(pipe); in ironlake_fdi_disable()
2895 reg = FDI_RX_CTL(pipe); in ironlake_fdi_disable()
2898 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; in ironlake_fdi_disable()
2906 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); in ironlake_fdi_disable()
2910 reg = FDI_TX_CTL(pipe); in ironlake_fdi_disable()
2916 reg = FDI_RX_CTL(pipe); in ironlake_fdi_disable()
2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; in ironlake_fdi_disable()
3095 int pipe = intel_crtc->pipe; in ironlake_pch_enable() local
3098 assert_transcoder_disabled(dev_priv, pipe); in ironlake_pch_enable()
3102 I915_WRITE(FDI_RX_TUSIZE1(pipe), in ironlake_pch_enable()
3103 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); in ironlake_pch_enable()
3121 switch (pipe) { in ironlake_pch_enable()
3144 assert_panel_unlocked(dev_priv, pipe); in ironlake_pch_enable()
3145 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); in ironlake_pch_enable()
3146 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); in ironlake_pch_enable()
3147 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); in ironlake_pch_enable()
3149 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); in ironlake_pch_enable()
3150 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); in ironlake_pch_enable()
3151 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); in ironlake_pch_enable()
3152 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); in ironlake_pch_enable()
3160 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; in ironlake_pch_enable()
3161 reg = TRANS_DP_CTL(pipe); in ironlake_pch_enable()
3192 ironlake_enable_pch_transcoder(dev_priv, pipe); in ironlake_pch_enable()
3202 assert_transcoder_disabled(dev_priv, (enum pipe)TRANSCODER_A); in lpt_pch_enable()
3250 i = intel_crtc->pipe; in intel_get_pch_pll()
3291 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); in intel_get_pch_pll()
3306 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) in intel_cpt_verify_modeset() argument
3309 int dslreg = PIPEDSL(pipe); in intel_cpt_verify_modeset()
3316 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); in intel_cpt_verify_modeset()
3326 int pipe = intel_crtc->pipe; in ironlake_crtc_enable() local
3353 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
3354 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
3370 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | in ironlake_crtc_enable()
3371 PF_PIPE_SEL_IVB(pipe)); in ironlake_crtc_enable()
3373 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); in ironlake_crtc_enable()
3374 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); in ironlake_crtc_enable()
3375 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); in ironlake_crtc_enable()
3384 intel_enable_pipe(dev_priv, pipe, is_pch_port); in ironlake_crtc_enable()
3385 intel_enable_plane(dev_priv, plane, pipe); in ironlake_crtc_enable()
3400 intel_cpt_verify_modeset(dev, intel_crtc->pipe); in ironlake_crtc_enable()
3410 intel_wait_for_vblank(dev, intel_crtc->pipe); in ironlake_crtc_enable()
3419 int pipe = intel_crtc->pipe; in haswell_crtc_enable() local
3449 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | in haswell_crtc_enable()
3450 PF_PIPE_SEL_IVB(pipe)); in haswell_crtc_enable()
3451 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); in haswell_crtc_enable()
3452 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); in haswell_crtc_enable()
3464 intel_enable_pipe(dev_priv, pipe, is_pch_port); in haswell_crtc_enable()
3465 intel_enable_plane(dev_priv, plane, pipe); in haswell_crtc_enable()
3487 intel_wait_for_vblank(dev, intel_crtc->pipe); in haswell_crtc_enable()
3496 int pipe = intel_crtc->pipe; in ironlake_crtc_disable() local
3508 drm_vblank_off(dev, pipe); in ironlake_crtc_disable()
3511 intel_disable_plane(dev_priv, plane, pipe); in ironlake_crtc_disable()
3516 intel_disable_pipe(dev_priv, pipe); in ironlake_crtc_disable()
3519 I915_WRITE(PF_CTL(pipe), 0); in ironlake_crtc_disable()
3520 I915_WRITE(PF_WIN_SZ(pipe), 0); in ironlake_crtc_disable()
3528 ironlake_disable_pch_transcoder(dev_priv, pipe); in ironlake_crtc_disable()
3532 reg = TRANS_DP_CTL(pipe); in ironlake_crtc_disable()
3540 switch (pipe) { in ironlake_crtc_disable()
3576 int pipe = intel_crtc->pipe; in haswell_crtc_disable() local
3590 drm_vblank_off(dev, pipe); in haswell_crtc_disable()
3593 intel_disable_plane(dev_priv, plane, pipe); in haswell_crtc_disable()
3598 intel_disable_pipe(dev_priv, pipe); in haswell_crtc_disable()
3603 I915_WRITE(PF_CTL(pipe), 0); in haswell_crtc_disable()
3604 I915_WRITE(PF_WIN_SZ(pipe), 0); in haswell_crtc_disable()
3637 intel_crtc->cpu_transcoder = (enum transcoder)intel_crtc->pipe; in haswell_crtc_off()
3666 int pipe = intel_crtc->pipe; in i9xx_crtc_enable() local
3677 intel_enable_pll(dev_priv, pipe); in i9xx_crtc_enable()
3678 intel_enable_pipe(dev_priv, pipe, false); in i9xx_crtc_enable()
3679 intel_enable_plane(dev_priv, plane, pipe); in i9xx_crtc_enable()
3698 int pipe = intel_crtc->pipe; in i9xx_crtc_disable() local
3711 drm_vblank_off(dev, pipe); in i9xx_crtc_disable()
3718 intel_disable_plane(dev_priv, plane, pipe); in i9xx_crtc_disable()
3719 intel_disable_pipe(dev_priv, pipe); in i9xx_crtc_disable()
3724 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe) in i9xx_crtc_disable()
3727 intel_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
3744 int pipe = intel_crtc->pipe; in intel_crtc_update_sarea() local
3753 switch (pipe) { in intel_crtc_update_sarea()
3763 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); in intel_crtc_update_sarea()
3807 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); in intel_crtc_disable()
3875 enum pipe pipe; in intel_connector_check_state() local
3888 encoder_enabled = encoder->get_hw_state(encoder, &pipe); in intel_connector_check_state()
3897 WARN(pipe != to_intel_crtc(crtc)->pipe, in intel_connector_check_state()
3931 enum pipe pipe = 0; in intel_connector_get_hw_state() local
3934 return encoder->get_hw_state(encoder, &pipe); in intel_connector_get_hw_state()
4284 int pipe = intel_crtc->pipe; in i9xx_update_pll_dividers() local
4299 I915_WRITE(FP0(pipe), fp); in i9xx_update_pll_dividers()
4304 I915_WRITE(FP1(pipe), fp2); in i9xx_update_pll_dividers()
4307 I915_WRITE(FP1(pipe), fp); in i9xx_update_pll_dividers()
4317 int pipe = intel_crtc->pipe; in intel_update_lvds() local
4322 if (pipe == 1) { in intel_update_lvds()
4365 int pipe = intel_crtc->pipe; in vlv_update_pll() local
4379 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()
4380 POSTING_READ(DPLL(pipe)); in vlv_update_pll()
4398 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); in vlv_update_pll()
4400 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); in vlv_update_pll()
4406 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); in vlv_update_pll()
4408 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); in vlv_update_pll()
4411 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()
4412 POSTING_READ(DPLL(pipe)); in vlv_update_pll()
4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in vlv_update_pll()
4414 DRM_ERROR("DPLL %d failed to lock\n", pipe); in vlv_update_pll()
4421 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()
4424 POSTING_READ(DPLL(pipe)); in vlv_update_pll()
4435 I915_WRITE(DPLL_MD(pipe), temp); in vlv_update_pll()
4436 POSTING_READ(DPLL_MD(pipe)); in vlv_update_pll()
4443 if(pipe == 1) in vlv_update_pll()
4450 if(pipe == 1) in vlv_update_pll()
4465 int pipe = intel_crtc->pipe; in i9xx_update_pll() local
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); in i9xx_update_pll()
4530 POSTING_READ(DPLL(pipe)); in i9xx_update_pll()
4543 I915_WRITE(DPLL(pipe), dpll); in i9xx_update_pll()
4546 POSTING_READ(DPLL(pipe)); in i9xx_update_pll()
4558 I915_WRITE(DPLL_MD(pipe), temp); in i9xx_update_pll()
4565 I915_WRITE(DPLL(pipe), dpll); in i9xx_update_pll()
4577 int pipe = intel_crtc->pipe; in i8xx_update_pll() local
4606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); in i8xx_update_pll()
4607 POSTING_READ(DPLL(pipe)); in i8xx_update_pll()
4617 I915_WRITE(DPLL(pipe), dpll); in i8xx_update_pll()
4620 POSTING_READ(DPLL(pipe)); in i8xx_update_pll()
4628 I915_WRITE(DPLL(pipe), dpll); in i8xx_update_pll()
4637 enum pipe pipe = intel_crtc->pipe; in intel_set_pipe_timings() local
4679 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_pipe_timings()
4680 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); in intel_set_pipe_timings()
4685 I915_WRITE(PIPESRC(pipe), in intel_set_pipe_timings()
4698 int pipe = intel_crtc->pipe; in i9xx_crtc_mode_set() local
4780 pipeconf = I915_READ(PIPECONF(pipe)); in i9xx_crtc_mode_set()
4785 if (pipe == 0) in i9xx_crtc_mode_set()
4790 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { in i9xx_crtc_mode_set()
4822 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); in i9xx_crtc_mode_set()
4852 I915_WRITE(PIPECONF(pipe), pipeconf); in i9xx_crtc_mode_set()
4853 POSTING_READ(PIPECONF(pipe)); in i9xx_crtc_mode_set()
4854 intel_enable_pipe(dev_priv, pipe, false); in i9xx_crtc_mode_set()
4856 intel_wait_for_vblank(dev, pipe); in i9xx_crtc_mode_set()
5194 int pipe = intel_crtc->pipe; in ironlake_set_pipeconf() local
5197 val = I915_READ(PIPECONF(pipe)); in ironlake_set_pipeconf()
5228 I915_WRITE(PIPECONF(pipe), val); in ironlake_set_pipeconf()
5229 POSTING_READ(PIPECONF(pipe)); in ironlake_set_pipeconf()
5346 intel_crtc->pipe, intel_crtc->fdi_lanes); in ironlake_check_fdi_lanes()
5349 intel_crtc->pipe, intel_crtc->fdi_lanes); in ironlake_check_fdi_lanes()
5359 switch (intel_crtc->pipe) { in ironlake_check_fdi_lanes()
5366 intel_crtc->pipe, intel_crtc->fdi_lanes); in ironlake_check_fdi_lanes()
5383 intel_crtc->pipe, intel_crtc->fdi_lanes); in ironlake_check_fdi_lanes()
5595 int pipe = intel_crtc->pipe; in ironlake_crtc_mode_set() local
5651 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); in ironlake_crtc_mode_set()
5661 pipe); in ironlake_crtc_mode_set()
5676 temp |= PORT_TRANS_SEL_CPT(pipe); in ironlake_crtc_mode_set()
5678 if (pipe == 1) in ironlake_crtc_mode_set()
5710 I915_WRITE(TRANSDATA_M1(pipe), 0); in ironlake_crtc_mode_set()
5711 I915_WRITE(TRANSDATA_N1(pipe), 0); in ironlake_crtc_mode_set()
5712 I915_WRITE(TRANSDPLINK_M1(pipe), 0); in ironlake_crtc_mode_set()
5713 I915_WRITE(TRANSDPLINK_N1(pipe), 0); in ironlake_crtc_mode_set()
5754 intel_wait_for_vblank(dev, pipe); in ironlake_crtc_mode_set()
5764 intel_update_linetime_watermarks(dev, pipe, adjusted_mode); in ironlake_crtc_mode_set()
5778 int pipe = intel_crtc->pipe; in haswell_crtc_mode_set() local
5811 intel_crtc->cpu_transcoder = pipe; in haswell_crtc_mode_set()
5818 num_connectors, pipe_name(pipe)); in haswell_crtc_mode_set()
5847 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); in haswell_crtc_mode_set()
5867 pipe); in haswell_crtc_mode_set()
5882 temp |= PORT_TRANS_SEL_CPT(pipe); in haswell_crtc_mode_set()
5884 if (pipe == 1) in haswell_crtc_mode_set()
5922 I915_WRITE(TRANSDATA_M1(pipe), 0); in haswell_crtc_mode_set()
5923 I915_WRITE(TRANSDATA_N1(pipe), 0); in haswell_crtc_mode_set()
5924 I915_WRITE(TRANSDPLINK_M1(pipe), 0); in haswell_crtc_mode_set()
5925 I915_WRITE(TRANSDPLINK_N1(pipe), 0); in haswell_crtc_mode_set()
5975 intel_update_linetime_watermarks(dev, pipe, adjusted_mode); in haswell_crtc_mode_set()
5991 int pipe = intel_crtc->pipe; in intel_crtc_mode_set() local
5994 drm_vblank_pre_modeset(dev, pipe); in intel_crtc_mode_set()
5998 drm_vblank_post_modeset(dev, pipe); in intel_crtc_mode_set()
6093 int pipe = to_intel_crtc(crtc)->pipe; in haswell_write_eld() local
6096 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); in haswell_write_eld()
6097 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); in haswell_write_eld()
6098 int aud_config = HSW_AUD_CFG(pipe); in haswell_write_eld()
6107 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); in haswell_write_eld()
6111 intel_wait_for_vblank(dev, pipe); in haswell_write_eld()
6116 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); in haswell_write_eld()
6128 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); in haswell_write_eld()
6130 eldv = AUDIO_ELD_VALID_A << (pipe * 4); in haswell_write_eld()
6181 int pipe = to_intel_crtc(crtc)->pipe; in ironlake_write_eld() local
6184 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); in ironlake_write_eld()
6185 aud_config = IBX_AUD_CFG(pipe); in ironlake_write_eld()
6186 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); in ironlake_write_eld()
6189 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); in ironlake_write_eld()
6190 aud_config = CPT_AUD_CFG(pipe); in ironlake_write_eld()
6191 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); in ironlake_write_eld()
6195 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); in ironlake_write_eld()
6274 int palreg = PALETTE(intel_crtc->pipe); in intel_crtc_load_lut()
6283 palreg = LGC_PALETTE(intel_crtc->pipe); in intel_crtc_load_lut()
6328 int pipe = intel_crtc->pipe; in i9xx_update_cursor() local
6332 uint32_t cntl = I915_READ(CURCNTR(pipe)); in i9xx_update_cursor()
6336 cntl |= pipe << 28; /* Connect to correct pipe */ in i9xx_update_cursor()
6341 I915_WRITE(CURCNTR(pipe), cntl); in i9xx_update_cursor()
6346 I915_WRITE(CURBASE(pipe), base); in i9xx_update_cursor()
6354 int pipe = intel_crtc->pipe; in ivb_update_cursor() local
6358 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); in ivb_update_cursor()
6366 I915_WRITE(CURCNTR_IVB(pipe), cntl); in ivb_update_cursor()
6371 I915_WRITE(CURBASE_IVB(pipe), base); in ivb_update_cursor()
6381 int pipe = intel_crtc->pipe; in intel_crtc_update_cursor() local
6422 I915_WRITE(CURPOS_IVB(pipe), pos); in intel_crtc_update_cursor()
6425 I915_WRITE(CURPOS(pipe), pos); in intel_crtc_update_cursor()
6495 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, in intel_crtc_cursor_set()
6794 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_get_load_detect_pipe()
6832 int pipe = intel_crtc->pipe; in intel_crtc_clock_get() local
6833 u32 dpll = I915_READ(DPLL(pipe)); in intel_crtc_clock_get()
6838 fp = I915_READ(FP0(pipe)); in intel_crtc_clock_get()
6840 fp = I915_READ(FP1(pipe)); in intel_crtc_clock_get()
6877 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); in intel_crtc_clock_get()
6951 int pipe = intel_crtc->pipe; in intel_increase_pllclock() local
6952 int dpll_reg = DPLL(pipe); in intel_increase_pllclock()
6965 assert_panel_unlocked(dev_priv, pipe); in intel_increase_pllclock()
6969 intel_wait_for_vblank(dev, pipe); in intel_increase_pllclock()
6994 int pipe = intel_crtc->pipe; in intel_decrease_pllclock() local
6995 int dpll_reg = DPLL(pipe); in intel_decrease_pllclock()
7000 assert_panel_unlocked(dev_priv, pipe); in intel_decrease_pllclock()
7005 intel_wait_for_vblank(dev, pipe); in intel_decrease_pllclock()
7122 drm_send_vblank_event(dev, intel_crtc->pipe, work->event); in do_intel_finish_page_flip()
7124 drm_vblank_put(dev, intel_crtc->pipe); in do_intel_finish_page_flip()
7140 void intel_finish_page_flip(struct drm_device *dev, int pipe) in intel_finish_page_flip() argument
7143 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_finish_page_flip()
7301 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen4_queue_flip()
7345 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen6_queue_flip()
7456 ret = drm_vblank_get(dev, intel_crtc->pipe); in intel_crtc_page_flip()
7465 drm_vblank_put(dev, intel_crtc->pipe); in intel_crtc_page_flip()
7521 drm_vblank_put(dev, intel_crtc->pipe); in intel_crtc_page_flip()
7693 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; in intel_modeset_affected_pipes()
7698 1 << connector->new_encoder->new_crtc->pipe; in intel_modeset_affected_pipes()
7709 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; in intel_modeset_affected_pipes()
7713 *prepare_pipes |= 1 << encoder->new_crtc->pipe; in intel_modeset_affected_pipes()
7732 *disable_pipes |= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
7739 *prepare_pipes |= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
7758 *modeset_pipes &= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
7759 *prepare_pipes &= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
7788 if (prepare_pipes & (1 << intel_crtc->pipe)) in intel_modeset_update_state()
7806 if (prepare_pipes & (1 << intel_crtc->pipe)) { in intel_modeset_update_state()
7826 if (mask & (1 <<(intel_crtc)->pipe)) \
7849 enum pipe pipe, tracked_pipe; in intel_modeset_check_state() local
7879 active = encoder->get_hw_state(encoder, &pipe); in intel_modeset_check_state()
7888 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; in intel_modeset_check_state()
7889 WARN(active && pipe != tracked_pipe, in intel_modeset_check_state()
7892 tracked_pipe, pipe); in intel_modeset_check_state()
7922 assert_pipe(dev->dev_private, crtc->pipe, crtc->active); in intel_modeset_check_state()
8346 static void intel_crtc_init(struct drm_device *dev, int pipe) in intel_crtc_init() argument
8366 intel_crtc->pipe = pipe; in intel_crtc_init()
8367 intel_crtc->plane = pipe; in intel_crtc_init()
8368 intel_crtc->cpu_transcoder = pipe; in intel_crtc_init()
8371 intel_crtc->plane = !pipe; in intel_crtc_init()
8374 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || in intel_crtc_init()
8377 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; in intel_crtc_init()
8403 pipe_from_crtc_id->pipe = crtc->pipe; in intel_get_pipe_from_crtc_id()
9098 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) in intel_check_plane_mapping()
9146 crtc->pipe == PIPE_A && !crtc->active) { in intel_sanitize_crtc()
9251 enum pipe pipe; in intel_modeset_setup_hw_state() local
9264 pipe = PIPE_A; in intel_modeset_setup_hw_state()
9267 pipe = PIPE_B; in intel_modeset_setup_hw_state()
9270 pipe = PIPE_C; in intel_modeset_setup_hw_state()
9274 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
9278 pipe_name(pipe)); in intel_modeset_setup_hw_state()
9282 for_each_pipe(pipe) { in intel_modeset_setup_hw_state()
9283 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
9303 pipe = 0; in intel_modeset_setup_hw_state()
9305 if (encoder->get_hw_state(encoder, &pipe)) { in intel_modeset_setup_hw_state()
9307 dev_priv->pipe_to_crtc_mapping[pipe]; in intel_modeset_setup_hw_state()
9317 pipe); in intel_modeset_setup_hw_state()
9342 for_each_pipe(pipe) { in intel_modeset_setup_hw_state()
9343 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
9348 for_each_pipe(pipe) { in intel_modeset_setup_hw_state()
9349 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
9476 } pipe[I915_MAX_PIPES]; member
9518 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder)); in intel_display_capture_error_state()
9519 error->pipe[i].source = I915_READ(PIPESRC(i)); in intel_display_capture_error_state()
9520 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); in intel_display_capture_error_state()
9521 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder)); in intel_display_capture_error_state()
9522 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_display_capture_error_state()
9523 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); in intel_display_capture_error_state()
9524 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder)); in intel_display_capture_error_state()
9525 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); in intel_display_capture_error_state()
9542 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); in intel_display_print_error_state()
9543 seq_printf(m, " SRC: %08x\n", error->pipe[i].source); in intel_display_print_error_state()
9544 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); in intel_display_print_error_state()
9545 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); in intel_display_print_error_state()
9546 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); in intel_display_print_error_state()
9547 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); in intel_display_print_error_state()
9548 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); in intel_display_print_error_state()
9549 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); in intel_display_print_error_state()