462 	POSTING_READ(DPIO_CTL);  in vlv_init_dpio()
464 	POSTING_READ(DPIO_CTL);  in vlv_init_dpio()
1461 	POSTING_READ(reg);  in intel_enable_pll()
1464 	POSTING_READ(reg);  in intel_enable_pll()
1467 	POSTING_READ(reg);  in intel_enable_pll()
1496 	POSTING_READ(reg);  in intel_disable_pll()
1606 	POSTING_READ(reg);  in ironlake_enable_pch_pll()
1650 	POSTING_READ(reg);  in intel_disable_pch_pll()
2127 	POSTING_READ(reg);  in i9xx_update_plane()
2218 	POSTING_READ(reg);  in ironlake_update_plane()
2392 	POSTING_READ(DP_A);  in ironlake_set_pll_edp()
2428 	POSTING_READ(reg);  in intel_fdi_normal_train()
2499 	POSTING_READ(reg);  in ironlake_fdi_link_train()
2534 	POSTING_READ(reg);  in ironlake_fdi_link_train()
2579 	POSTING_READ(reg);  in gen6_fdi_link_train()
2608 	POSTING_READ(reg);  in gen6_fdi_link_train()
2618 		POSTING_READ(reg);  in gen6_fdi_link_train()
2661 	POSTING_READ(reg);  in gen6_fdi_link_train()
2671 		POSTING_READ(reg);  in gen6_fdi_link_train()
2711 	POSTING_READ(reg);  in ivb_manual_fdi_link_train()
2740 	POSTING_READ(reg);  in ivb_manual_fdi_link_train()
2750 		POSTING_READ(reg);  in ivb_manual_fdi_link_train()
2782 	POSTING_READ(reg);  in ivb_manual_fdi_link_train()
2792 		POSTING_READ(reg);  in ivb_manual_fdi_link_train()
2827 	POSTING_READ(reg);  in ironlake_fdi_pll_enable()
2834 	POSTING_READ(reg);  in ironlake_fdi_pll_enable()
2846 			POSTING_READ(reg);  in ironlake_fdi_pll_enable()
2869 	POSTING_READ(reg);  in ironlake_fdi_pll_disable()
2877 	POSTING_READ(reg);  in ironlake_fdi_pll_disable()
2893 	POSTING_READ(reg);  in ironlake_fdi_disable()
2901 	POSTING_READ(reg);  in ironlake_fdi_disable()
2930 	POSTING_READ(reg);  in ironlake_fdi_disable()
3297 	POSTING_READ(pll->pll_reg);  in intel_get_pch_pll()
4380 	POSTING_READ(DPLL(pipe));  in vlv_update_pll()
4412 	POSTING_READ(DPLL(pipe));  in vlv_update_pll()
4424 	POSTING_READ(DPLL(pipe));  in vlv_update_pll()
4436 	POSTING_READ(DPLL_MD(pipe));  in vlv_update_pll()
4530 	POSTING_READ(DPLL(pipe));  in i9xx_update_pll()
4546 	POSTING_READ(DPLL(pipe));  in i9xx_update_pll()
4607 	POSTING_READ(DPLL(pipe));  in i8xx_update_pll()
4620 	POSTING_READ(DPLL(pipe));  in i8xx_update_pll()
4853 	POSTING_READ(PIPECONF(pipe));  in i9xx_crtc_mode_set()
4859 	POSTING_READ(DSPCNTR(plane));  in i9xx_crtc_mode_set()
4938 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
4955 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
4966 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
4977 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
5229 	POSTING_READ(PIPECONF(pipe));  in ironlake_set_pipeconf()
5254 	POSTING_READ(PIPECONF(cpu_transcoder));  in haswell_set_pipeconf()
5335 	POSTING_READ(SOUTH_CHICKEN1);  in cpt_enable_fdi_bc_bifurcation()
5720 		POSTING_READ(intel_crtc->pch_pll->pll_reg);  in ironlake_crtc_mode_set()
5758 	POSTING_READ(DSPCNTR(plane));  in ironlake_crtc_mode_set()
5935 			POSTING_READ(intel_crtc->pch_pll->pll_reg);  in haswell_crtc_mode_set()
5969 	POSTING_READ(DSPCNTR(plane));  in haswell_crtc_mode_set()
8979 	POSTING_READ(vga_reg);  in i915_disable_vga()
9241 		POSTING_READ(vga_reg);  in i915_redisable_vga()