Lines Matching refs:DPLL
1055 reg = DPLL(pipe); in assert_pll()
1455 reg = DPLL(pipe); in intel_enable_pll()
1492 reg = DPLL(pipe); in intel_disable_pll()
4379 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()
4380 POSTING_READ(DPLL(pipe)); in vlv_update_pll()
4411 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()
4412 POSTING_READ(DPLL(pipe)); in vlv_update_pll()
4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in vlv_update_pll()
4421 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()
4424 POSTING_READ(DPLL(pipe)); in vlv_update_pll()
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); in i9xx_update_pll()
4530 POSTING_READ(DPLL(pipe)); in i9xx_update_pll()
4543 I915_WRITE(DPLL(pipe), dpll); in i9xx_update_pll()
4546 POSTING_READ(DPLL(pipe)); in i9xx_update_pll()
4565 I915_WRITE(DPLL(pipe), dpll); in i9xx_update_pll()
4606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); in i8xx_update_pll()
4607 POSTING_READ(DPLL(pipe)); in i8xx_update_pll()
4617 I915_WRITE(DPLL(pipe), dpll); in i8xx_update_pll()
4620 POSTING_READ(DPLL(pipe)); in i8xx_update_pll()
4628 I915_WRITE(DPLL(pipe), dpll); in i8xx_update_pll()
6833 u32 dpll = I915_READ(DPLL(pipe)); in intel_crtc_clock_get()
6952 int dpll_reg = DPLL(pipe); in intel_increase_pllclock()
6995 int dpll_reg = DPLL(pipe); in intel_decrease_pllclock()