32 void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv,  in savage_emit_clip_rect_s3d()  argument
35 	uint32_t scstart = dev_priv->state.s3d.new_scstart;  in savage_emit_clip_rect_s3d()
36 	uint32_t scend = dev_priv->state.s3d.new_scend;  in savage_emit_clip_rect_s3d()
43 	if (scstart != dev_priv->state.s3d.scstart ||  in savage_emit_clip_rect_s3d()
44 	    scend   != dev_priv->state.s3d.scend) {  in savage_emit_clip_rect_s3d()
51 		dev_priv->state.s3d.scstart = scstart;  in savage_emit_clip_rect_s3d()
52 		dev_priv->state.s3d.scend = scend;  in savage_emit_clip_rect_s3d()
53 		dev_priv->waiting = 1;  in savage_emit_clip_rect_s3d()
58 void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,  in savage_emit_clip_rect_s4()  argument
61 	uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0;  in savage_emit_clip_rect_s4()
62 	uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1;  in savage_emit_clip_rect_s4()
69 	if (drawctrl0 != dev_priv->state.s4.drawctrl0 ||  in savage_emit_clip_rect_s4()
70 	    drawctrl1 != dev_priv->state.s4.drawctrl1) {  in savage_emit_clip_rect_s4()
77 		dev_priv->state.s4.drawctrl0 = drawctrl0;  in savage_emit_clip_rect_s4()
78 		dev_priv->state.s4.drawctrl1 = drawctrl1;  in savage_emit_clip_rect_s4()
79 		dev_priv->waiting = 1;  in savage_emit_clip_rect_s4()
84 static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit,  in savage_verify_texaddr()  argument
93 		if (addr < dev_priv->texture_offset ||  in savage_verify_texaddr()
94 		    addr >= dev_priv->texture_offset + dev_priv->texture_size) {  in savage_verify_texaddr()
101 		if (!dev_priv->agp_textures) {  in savage_verify_texaddr()
107 		if (addr < dev_priv->agp_textures->offset ||  in savage_verify_texaddr()
108 		    addr >= (dev_priv->agp_textures->offset +  in savage_verify_texaddr()
109 			     dev_priv->agp_textures->size)) {  in savage_verify_texaddr()
121 		dev_priv->state.where = regs[reg - start]
126 		dev_priv->state.where = (tmp & (mask)) |	\
127 			(dev_priv->state.where & ~(mask));	\
130 static int savage_verify_state_s3d(drm_savage_private_t *dev_priv,  in savage_verify_state_s3d()  argument
152 		if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK)  in savage_verify_state_s3d()
153 			return savage_verify_texaddr(dev_priv, 0,  in savage_verify_state_s3d()
154 						dev_priv->state.s3d.texaddr);  in savage_verify_state_s3d()
160 static int savage_verify_state_s4(drm_savage_private_t *dev_priv,  in savage_verify_state_s4()  argument
185 		if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK)  in savage_verify_state_s4()
186 			ret |= savage_verify_texaddr(dev_priv, 0,  in savage_verify_state_s4()
187 						dev_priv->state.s4.texaddr0);  in savage_verify_state_s4()
188 		if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK)  in savage_verify_state_s4()
189 			ret |= savage_verify_texaddr(dev_priv, 1,  in savage_verify_state_s4()
190 						dev_priv->state.s4.texaddr1);  in savage_verify_state_s4()
198 static int savage_dispatch_state(drm_savage_private_t *dev_priv,  in savage_dispatch_state()  argument
212 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_state()
213 		ret = savage_verify_state_s3d(dev_priv, start, count, regs);  in savage_dispatch_state()
230 		ret = savage_verify_state_s4(dev_priv, start, count, regs);  in savage_dispatch_state()
254 		dev_priv->waiting = 1;  in savage_dispatch_state()
279 static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,  in savage_dispatch_dma_prim()  argument
324 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_dma_prim()
354 	if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {  in savage_dispatch_dma_prim()
357 		BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);  in savage_dispatch_dma_prim()
358 		dev_priv->state.common.vbaddr = dmabuf->bus_address;  in savage_dispatch_dma_prim()
360 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {  in savage_dispatch_dma_prim()
369 		dev_priv->waiting = 0;  in savage_dispatch_dma_prim()
392 		} else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_dma_prim()
419 static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv,  in savage_dispatch_vb_prim()  argument
461 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_vb_prim()
537 static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,  in savage_dispatch_dma_idx()  argument
580 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_dma_idx()
604 	if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {  in savage_dispatch_dma_idx()
607 		BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);  in savage_dispatch_dma_idx()
608 		dev_priv->state.common.vbaddr = dmabuf->bus_address;  in savage_dispatch_dma_idx()
610 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {  in savage_dispatch_dma_idx()
619 		dev_priv->waiting = 0;  in savage_dispatch_dma_idx()
651 		} else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_dma_idx()
678 static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv,  in savage_dispatch_vb_idx()  argument
718 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_vb_idx()
792 static int savage_dispatch_clear(drm_savage_private_t *dev_priv,  in savage_dispatch_clear()  argument
836 				DMA_WRITE(dev_priv->front_offset);  in savage_dispatch_clear()
837 				DMA_WRITE(dev_priv->front_bd);  in savage_dispatch_clear()
840 				DMA_WRITE(dev_priv->back_offset);  in savage_dispatch_clear()
841 				DMA_WRITE(dev_priv->back_bd);  in savage_dispatch_clear()
844 				DMA_WRITE(dev_priv->depth_offset);  in savage_dispatch_clear()
845 				DMA_WRITE(dev_priv->depth_bd);  in savage_dispatch_clear()
865 static int savage_dispatch_swap(drm_savage_private_t *dev_priv,  in savage_dispatch_swap()  argument
882 		DMA_WRITE(dev_priv->back_offset);  in savage_dispatch_swap()
883 		DMA_WRITE(dev_priv->back_bd);  in savage_dispatch_swap()
894 static int savage_dispatch_draw(drm_savage_private_t *dev_priv,  in savage_dispatch_draw()  argument
908 		dev_priv->emit_clip_rect(dev_priv, &boxes[i]);  in savage_dispatch_draw()
918 					dev_priv, &cmd_header, dmabuf);  in savage_dispatch_draw()
922 					dev_priv, &cmd_header,  in savage_dispatch_draw()
928 				ret = savage_dispatch_dma_idx(dev_priv,  in savage_dispatch_draw()
936 				ret = savage_dispatch_vb_idx(dev_priv,  in savage_dispatch_draw()
960 	drm_savage_private_t *dev_priv = dev->dev_private;  in savage_bci_cmdbuf()  local
1043 	dev_priv->waiting = 1;  in savage_bci_cmdbuf()
1077 					dev_priv, first_draw_cmd,  in savage_bci_cmdbuf()
1101 			ret = savage_dispatch_state(dev_priv, &cmd_header,  in savage_bci_cmdbuf()
1114 			ret = savage_dispatch_clear(dev_priv, &cmd_header,  in savage_bci_cmdbuf()
1122 			ret = savage_dispatch_swap(dev_priv, cmdbuf->nbox,  in savage_bci_cmdbuf()
1141 			dev_priv, first_draw_cmd, cmdbuf->cmd_addr, dmabuf,  in savage_bci_cmdbuf()
1155 		event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);  in savage_bci_cmdbuf()
1156 		SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);  in savage_bci_cmdbuf()