136 	outb (BCR0(b->port), 0);  in ct_close_board()
370 	outb (c->IE1, inb (c->IE1) | IE1_CDCDE);  in ct_start_chan()
371 	outb (c->IE0, inb (c->IE0) | IE0_RX_INTE);  in ct_start_chan()
374 	outb (IER0(c->board->port), ier0);  in ct_start_chan()
381 	outb (c->TX.DIR, DIR_CHAIN_EOME | DIR_CHAIN_BOFE | DIR_CHAIN_COFE);  in ct_start_chan()
402 		outb (c->IE1, inb (c->IE1) | IE1_CDCDE);  in ct_enable_receive()
403 		outb (c->IE0, inb (c->IE0) | IE0_RX_INTE);  in ct_enable_receive()
406 		outb (IER0(c->board->port), ier0);  in ct_enable_receive()
410 		outb (c->CMD, CMD_RX_DISABLE);  in ct_enable_receive()
415 		outb (IER0(c->board->port), ier0);  in ct_enable_receive()
420 		outb (IER1(c->board->port), ier1);  in ct_enable_receive()
439 		outb (c->TX.DIR,  in ct_enable_transmit()
442 		outb (c->CMD, CMD_TX_DISABLE);  in ct_enable_transmit()
447 		outb (IER0(c->board->port), ier0);  in ct_enable_transmit()
452 		outb (IER1(c->board->port), ier1);  in ct_enable_transmit()
506 	outb (c->MD2, *(unsigned char*)&c->opt.md2);  in ct_set_nrzi()
516 	outb (BCR2(c->board->port), c->board->bcr2);  in ct_set_invtxc()
531 	outb (BCR2(c->board->port), c->board->bcr2);  in ct_set_invrxc()
549 			outb (BCR1(b->port), b->bcr1);  in ct_int_handler()
648 	outb (GERR (c->board->port), bpv);  in ct_g703_timer()
651 	outb (GERR (c->board->port), tsterr);  in ct_g703_timer()
655 	outb (GLDR (c->board->port), tstreq);  in ct_g703_timer()
927 			outb (c->RX.DSR, dsr);  in ct_hdlc_interrupt()
929 			outb (c->RX.DSR, (dsr & 0xfc) | DSR_DMA_ENABLE);  in ct_hdlc_interrupt()
943 		outb (c->ST1, st1);  in ct_hdlc_interrupt()
944 		outb (c->ST2, st2);  in ct_hdlc_interrupt()
963 		outb (c->RX.DSR, dsr);  in ct_hdlc_interrupt()
990 			outb (c->TX.DSR, DSR_CHAIN_EOM | DSR_DMA_CONTINUE);  in ct_hdlc_interrupt()
992 		outb (c->TX.DSR, dsr & ~DSR_CHAIN_EOM);  in ct_hdlc_interrupt()
1003 		outb (c->ST1, st1);  in ct_hdlc_interrupt()
1059 		outb (c->TX.DSR, DSR_DMA_ENABLE);  in ct_send_packet()