Lines Matching refs:outb
91 outb (BCR1(port), cr1); in ct_download()
93 outb (BCR0(port), BCR0_TCK); in ct_download()
94 outb (BCR0(port), 0); in ct_download()
144 #define nconfig_set(b) outb (bcr1_port, (bcr1 &= ~BCR1_NCONFIGI))
145 #define nconfig_clr(b) outb (bcr1_port, (bcr1 |= BCR1_NCONFIGI))
147 #define dclk_tick(b) outb (BCR3(b), 0)
151 outb (bcr1_port, bcr1); \
265 outb (BCR0(port), 0); in ct_probe2_board()
301 outb (BCR0(port), 0); in ct_probe_board()
316 outb (0x20, 0x0a); in ct_probe_irq()
318 outb (0xa0, 0x0a); in ct_probe_irq()
322 outb (BCR0(b->port), BCR0_HDRUN | irqmask[irq]); in ct_probe_irq()
323 outb (R(b->port,HD_TEPR_0R), 0); in ct_probe_irq()
326 outb (R(b->port,HD_TCSR_0R), TCSR_ENABLE | TCSR_INTR); in ct_probe_irq()
327 outb (IER2(b->port), IER2_RX_TME_0); in ct_probe_irq()
329 outb (BCR0(b->port), BCR0_HDRUN | irqmask[-irq]); in ct_probe_irq()
330 outb (IER0(b->port), 0); in ct_probe_irq()
331 outb (IER1(b->port), 0); in ct_probe_irq()
332 outb (IER2(b->port), 0); in ct_probe_irq()
333 outb (R(b->port,HD_TCSR_0R), 0); in ct_probe_irq()
337 outb (0xa0, 0x60 | ((-irq) & 7)); in ct_probe_irq()
338 outb (0x20, 0x62); in ct_probe_irq()
340 outb (0x20, 0x60 | (-irq)); in ct_probe_irq()
342 outb (BCR0(b->port), b->bcr0); in ct_probe_irq()
843 outb (E1CFG (b->port), b->e1cfg); in ct_setup_e1()
858 outb (E1CFG (b->port), b->e1cfg); in ct_setup_e1()
918 outb (GMD0(b->port), b->gmd0); in ct_setup_g703()
919 outb (GMD1(b->port), b->gmd1 | GMD1_NCS0 | GMD1_NCS1); in ct_setup_g703()
923 outb (GMD2(b->port), b->gmd2); in ct_setup_g703()
940 outb (GERR(b->port), 0xff); in ct_setup_g703()
941 outb (GLDR(b->port), 0xff); in ct_setup_g703()
953 outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR); in ct_setup_board()
956 outb (BCR0(b->port), 0); in ct_setup_board()
969 outb (BCR0(b->port), BCR0_HDRUN); in ct_setup_board()
970 outb (BCR0(b->port), b->bcr0); in ct_setup_board()
973 outb (BCR1(b->port), b->bcr1); in ct_setup_board()
977 outb (BCR2(b->port), b->bcr2); in ct_setup_board()
983 outb (WCRL(b->port), 0); in ct_setup_board()
984 outb (WCRM(b->port), 0); in ct_setup_board()
985 outb (WCRH(b->port), 0); in ct_setup_board()
988 outb (IMVR(b->port), 0); in ct_setup_board()
989 outb (ITCR(b->port), ITCR_CYCLE_SINGLE | ITCR_VECT_MOD); in ct_setup_board()
992 outb (IER0(b->port), 0); in ct_setup_board()
993 outb (IER1(b->port), 0); in ct_setup_board()
994 outb (IER2(b->port), 0); in ct_setup_board()
997 outb (PCR(b->port), BYTE b->opt.pcr); in ct_setup_board()
998 outb (DMER(b->port), DME_ENABLE); in ct_setup_board()
1001 outb (DMA_MODE, (b->dma & 3) | DMA_MODE_MASTER); in ct_setup_board()
1004 outb (DMA_MASK, b->dma & 3); in ct_setup_board()
1008 outb (GMD2(b->port), 0); in ct_setup_board()
1055 outb (c->MD0, BYTE amd0); in ct_update_chan()
1056 outb (c->MD1, BYTE amd1); in ct_update_chan()
1057 outb (c->CTL, c->rts ? 0 : CTL_RTS_INV); in ct_update_chan()
1070 outb (c->MD0, BYTE hmd0); in ct_update_chan()
1071 outb (c->MD1, BYTE c->hopt.md1); in ct_update_chan()
1072 outb (c->CTL, c->hopt.ctl & ~CTL_IDLE_PTRN); in ct_update_chan()
1073 outb (c->SA0, c->hopt.sa0); in ct_update_chan()
1074 outb (c->SA1, c->hopt.sa1); in ct_update_chan()
1075 outb (c->IDL, 0x7e); /* HDLC flag 01111110 */ in ct_update_chan()
1077 outb (c->MD0, BYTE c->hopt.md0); in ct_update_chan()
1078 outb (c->MD1, BYTE c->hopt.md1); in ct_update_chan()
1079 outb (c->SA0, c->hopt.sa0); in ct_update_chan()
1080 outb (c->SA1, c->hopt.sa1); in ct_update_chan()
1081 outb (c->IDL, 0x7e); /* HDLC flag 01111110 */ in ct_update_chan()
1084 outb (c->CTL, c->hopt.ctl & ~CTL_RTS_INV); in ct_update_chan()
1086 outb (c->CTL, c->hopt.ctl | CTL_RTS_INV); in ct_update_chan()
1094 outb (c->RX.DMR, dmr); in ct_update_chan()
1095 outb (c->TX.DMR, dmr); in ct_update_chan()
1099 outb (c->MD2, BYTE c->opt.md2); in ct_update_chan()
1122 outb (c->TMC, tmc); in ct_update_chan()
1123 outb (c->RXS, rxs); in ct_update_chan()
1130 outb (BCR1(c->board->port), c->board->bcr1); in ct_update_chan()
1131 outb (c->TXS, txs); in ct_update_chan()
1134 outb (BCR1(c->board->port), c->board->bcr1); in ct_update_chan()
1147 outb (c->RX.DSR, DSR_DMA_DISABLE); in ct_setup_chan()
1148 outb (c->TX.DSR, DSR_DMA_DISABLE); in ct_setup_chan()
1149 outb (c->CMD, CMD_TX_RESET); in ct_setup_chan()
1150 outb (c->CMD, CMD_TX_ABORT); in ct_setup_chan()
1151 outb (c->CMD, CMD_CHAN_RESET); in ct_setup_chan()
1154 outb (c->IE0, 0); in ct_setup_chan()
1155 outb (c->IE1, 0); in ct_setup_chan()
1156 outb (c->IE2, 0); in ct_setup_chan()
1157 outb (c->FIE, 0); in ct_setup_chan()
1220 outb (BCR1(c->board->port), c->board->bcr1 & ~txcout); in ct_enable_loop()
1222 outb (c->RXS, rxs | CLK_INT); in ct_enable_loop()
1223 outb (c->TXS, txs | CLK_INT); in ct_enable_loop()
1226 outb (BCR1(c->board->port), c->board->bcr1); in ct_enable_loop()
1228 outb (c->MD2, *(unsigned char*)&c->opt.md2); in ct_enable_loop()
1258 outb (BCR1(c->board->port), c->board->bcr1 & ~txcout); in ct_disable_loop()
1260 outb (c->RXS, rxs | CLK_LINE); in ct_disable_loop()
1262 outb (c->TXS, txs | CLK_INT); in ct_disable_loop()
1264 outb (c->TXS, txs | CLK_LINE); in ct_disable_loop()
1267 outb (BCR1(c->board->port), c->board->bcr1); in ct_disable_loop()
1269 outb (c->MD2, *(unsigned char*)&c->opt.md2); in ct_disable_loop()
1316 outb (c->MD0, BYTE c->hopt.md0); in ct_set_phony()
1317 outb (E1SYN(c->board->port), c->board->e1syn); in ct_set_phony()
1345 outb (c->RX.TEPR, TEPR_64); /* prescale to 16 kHz */ in ct_start_receiver()
1348 outb (c->RX.TCSR, TCSR_ENABLE | TCSR_INTR); in ct_start_receiver()
1353 outb (IER0(c->board->port), ier0); in ct_start_receiver()
1354 outb (IER1(c->board->port), ier1); in ct_start_receiver()
1355 outb (IER2(c->board->port), ier2); in ct_start_receiver()
1356 outb (c->IE0, ie0); in ct_start_receiver()
1357 outb (c->IE2, ie2); in ct_start_receiver()
1360 outb (c->RRC, dma ? c->opt.dma_rrc : c->opt.pio_rrc); in ct_start_receiver()
1364 outb (c->RX.DCR, DCR_ABORT); in ct_start_receiver()
1367 outb (c->RX.DARB, (unsigned char) (buf >> 16)); in ct_start_receiver()
1370 outb (c->RX.DIR, DIR_EOTE); in ct_start_receiver()
1373 outb (c->RX.SARB, (unsigned char) (desc >> 16)); in ct_start_receiver()
1377 outb (c->RX.DIR, DIR_CHAIN_EOME | DIR_CHAIN_BOFE | in ct_start_receiver()
1380 outb (c->RX.DSR, DSR_DMA_ENABLE); in ct_start_receiver()
1382 outb (c->CMD, CMD_RX_ENABLE); in ct_start_receiver()
1408 outb (IER0(c->board->port), ier0); in ct_start_transmitter()
1409 outb (IER1(c->board->port), ier1); in ct_start_transmitter()
1410 outb (c->IE0, ie0); in ct_start_transmitter()
1411 outb (c->IE1, ie1); in ct_start_transmitter()
1415 outb (c->TRC0, dma ? c->opt.dma_trc0 : c->opt.pio_trc0); in ct_start_transmitter()
1416 outb (c->TRC1, dma ? c->opt.dma_trc1 : c->opt.pio_trc1); in ct_start_transmitter()
1420 outb (c->TX.DCR, DCR_ABORT); in ct_start_transmitter()
1423 outb (c->TX.SARB, (unsigned char) (buf >> 16)); in ct_start_transmitter()
1426 outb (c->TX.DIR, DIR_EOTE); in ct_start_transmitter()
1429 outb (c->TX.SARB, (unsigned char) (desc >> 16)); in ct_start_transmitter()
1432 outb (c->TX.DIR, /* DIR_CHAIN_EOME | */ DIR_CHAIN_BOFE | in ct_start_transmitter()
1437 outb (c->CMD, CMD_TX_ENABLE); in ct_start_transmitter()
1441 outb (GERR(c->board->port), 0xff); in ct_start_transmitter()
1442 outb (GLDR(c->board->port), 0xff); in ct_start_transmitter()
1459 outb (BCR1(c->board->port), c->board->bcr1); in ct_set_dtr()
1470 outb (c->CTL, inb (c->CTL) & ~CTL_RTS_INV); in ct_set_rts()
1472 outb (c->CTL, inb (c->CTL) | CTL_RTS_INV); in ct_set_rts()
1484 outb (c->CTL, inb (c->CTL) | CTL_BRK); in ct_set_brk()
1486 outb (c->CTL, inb (c->CTL) & ~CTL_BRK); in ct_set_brk()
1558 outb (GMD2(b->port), b->gmd2); in ct_led()
1563 outb (E1CFG(b->port), b->e1cfg); in ct_led()
1571 outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR); in ct_disable_dma()
1597 outb (base, reg); in cte_in()
1603 outb (base, reg); in cte_out()
1604 outb (E1DAT (base & 0x3e0), val); in cte_out()
1616 outb (base, reg); outb (rw, mask); /* lock bits */ in cte_ins()
1617 outb (base, reg); val = inb (rw) & mask; /* get values */ in cte_ins()
1618 outb (base, reg); outb (rw, val); /* unlock bits */ in cte_ins()
1630 outb (E1CS2(base), E1CS2_SCC | reg >> 4); in cte_in2()
1631 outb (E1DAT(base), reg & 15); in cte_in2()
1637 outb (E1CS2(base), E1CS2_SCC | reg >> 4); in cte_out2()
1638 outb (E1DAT(base), reg & 15); in cte_out2()
1639 outb (E1DAT(base), val); in cte_out2()
1647 outb (E1CS2(c->board->port), E1CS2_SCC | E1CS2_DC | in cte_in2d()
1657 outb (E1CS2(c->board->port), E1CS2_SCC | (c->num ? 0 : E1CS2_AB)); in cte_out2c()
1658 outb (E1DAT(c->board->port), val); in cte_out2c()
1666 outb (E1CS2(c->board->port), E1CS2_SCC | E1CS2_DC | in cte_out2d()
1668 outb (E1DAT(c->board->port), val); in cte_out2d()
1685 outb (port, v); in ctg_output()
1686 outb (port, v); in ctg_output()
1687 outb (port, v); in ctg_output()
1688 outb (port, v); in ctg_output()
1689 outb (port, v | GMD0_SCLK); in ctg_output()
1690 outb (port, v | GMD0_SCLK); in ctg_output()
1691 outb (port, v | GMD0_SCLK); in ctg_output()
1692 outb (port, v | GMD0_SCLK); in ctg_output()
1694 outb (port, v0); in ctg_output()
1701 outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1); in ctg_outx()
1702 outb (GMD1(c->board->port), c->board->gmd1 | in ctg_outx()
1706 outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1); in ctg_outx()
1716 outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1); in ctg_inx()
1717 outb (GMD1(c->board->port), c->board->gmd1 | in ctg_inx()
1721 outb (port, c->board->gmd0 | GMD0_SCLK); in ctg_inx()
1724 outb (port, c->board->gmd0); in ctg_inx()
1726 outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1); in ctg_inx()