2252 				   params->phy[phy_index].mdio_ctrl);  in elink_set_mdio_emac_per_phy()
3422 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_write()
3423 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in elink_cl22_write()
3430 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl22_write()
3435 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_write()
3445 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in elink_cl22_write()
3458 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_read()
3459 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in elink_cl22_read()
3466 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl22_read()
3471 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_read()
3484 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in elink_cl22_read()
3501 		elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);  in elink_cl45_read()
3505 		elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_read()
3511 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl45_read()
3516 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_read()
3533 		REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl45_read()
3538 			val = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_read()
3563 		elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_read()
3578 		elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);  in elink_cl45_write()
3582 		elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_write()
3589 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl45_write()
3594 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_write()
3610 		REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl45_write()
3615 			tmp = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_write()
3638 		elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_write()
9204 	fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in elink_verify_sfp_module()
12432 	.mdio_ctrl	= 0,
12458 	.mdio_ctrl	= 0,
12493 	.mdio_ctrl	= 0,
12528 	.mdio_ctrl	= 0,
12568 	.mdio_ctrl	= 0,
12597 	.mdio_ctrl	= 0,
12628 	.mdio_ctrl	= 0,
12656 	.mdio_ctrl	= 0,
12687 	.mdio_ctrl	= 0,
12719 	.mdio_ctrl	= 0,
12749 	.mdio_ctrl	= 0,
12786 	.mdio_ctrl	= 0,
12824 	.mdio_ctrl	= 0,
12858 	.mdio_ctrl	= 0,
12892 	.mdio_ctrl	= 0,
12926 	.mdio_ctrl	= 0,
13144 	phy->mdio_ctrl = elink_get_emac_base(sc,  in elink_populate_int_phy()
13153 		   port, phy->addr, phy->mdio_ctrl);  in elink_populate_int_phy()
13267 	phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);  in elink_populate_ext_phy()
13283 		   phy->addr, phy->mdio_ctrl);  in elink_populate_ext_phy()