2265 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in elink_emac_init()
2268 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in elink_emac_init()
2340 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in elink_umac_enable()
2344 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in elink_umac_enable()
2455 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in elink_xmac_init()
2459 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in elink_xmac_init()
2485 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in elink_xmac_init()
2489 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in elink_xmac_init()
2603 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in elink_emac_enable()
2751 		REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in elink_emac_enable()
3233 		REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in elink_bmac_enable()
3238 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in elink_bmac_enable()
4160 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);  in elink_serdes_deassert()
4162 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);  in elink_serdes_deassert()
4196 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);  in elink_xgxs_deassert()
4198 	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);  in elink_xgxs_deassert()
7489 	REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,  in elink_int_link_reset()
13857 			REG_WR(sc, GRCBASE_MISC +  in elink_avoid_link_flap()
13861 			REG_WR(sc, GRCBASE_MISC +  in elink_avoid_link_flap()
14161 		REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in elink_link_reset()