174 	CSR_WRITE_2(sc, BM_MII_CSR, val);  in bm_mii_bitbang_write()
230 		CSR_WRITE_2(sc, BM_TX_CONFIG, reg);  in bm_miibus_statchg()
244 		CSR_WRITE_2(sc, BM_TX_CONFIG, reg);  in bm_miibus_statchg()
920 	CSR_WRITE_2(sc, BM_RX_CONFIG, reg);  in bm_setladrf()
927 		CSR_WRITE_2(sc, BM_RX_CONFIG, reg);  in bm_setladrf()
933 		CSR_WRITE_2(sc, BM_RX_CONFIG, reg);  in bm_setladrf()
960 	CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);  in bm_setladrf()
961 	CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);  in bm_setladrf()
962 	CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);  in bm_setladrf()
963 	CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]);  in bm_setladrf()
967 	CSR_WRITE_2(sc, BM_RX_CONFIG, reg);  in bm_setladrf()
974 	CSR_WRITE_2(sc, BM_RX_CONFIG, reg);  in bm_setladrf()
998 	CSR_WRITE_2(sc, BM_RX_RESET, 0x0000);  in bm_chip_setup()
999 	CSR_WRITE_2(sc, BM_TX_RESET, 0x0001);  in bm_chip_setup()
1007 	CSR_WRITE_2(sc,	BM_TX_RANDSEED, eaddr_sect[2]);  in bm_chip_setup()
1012 	CSR_WRITE_2(sc, BM_TX_IFC, reg);  in bm_chip_setup()
1026 	CSR_WRITE_2(sc, BM_TX_CONFIG, reg);  in bm_stop()
1030 	CSR_WRITE_2(sc, BM_RX_CONFIG, reg);  in bm_stop()
1123 	CSR_WRITE_2(sc, BM_TX_NCCNT, 0);  in bm_init_locked()
1124 	CSR_WRITE_2(sc, BM_TX_FCCNT, 0);  in bm_init_locked()
1125 	CSR_WRITE_2(sc, BM_TX_EXCNT, 0);  in bm_init_locked()
1126 	CSR_WRITE_2(sc, BM_TX_LTCNT, 0);  in bm_init_locked()
1129 	CSR_WRITE_2(sc, BM_RX_FRCNT, 0);  in bm_init_locked()
1130 	CSR_WRITE_2(sc, BM_RX_LECNT, 0);  in bm_init_locked()
1131 	CSR_WRITE_2(sc, BM_RX_AECNT, 0);  in bm_init_locked()
1132 	CSR_WRITE_2(sc, BM_RX_FECNT, 0);  in bm_init_locked()
1133 	CSR_WRITE_2(sc, BM_RXCV, 0);  in bm_init_locked()
1136 	CSR_WRITE_2(sc, BM_TX_THRESH, 0xff);  in bm_init_locked()
1138 	CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0);  in bm_init_locked()
1139 	CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001);  in bm_init_locked()
1142 	CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0);  in bm_init_locked()
1143 	CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001);  in bm_init_locked()
1149 	CSR_WRITE_2(sc, BM_HASHTAB0, 0);  in bm_init_locked()
1150 	CSR_WRITE_2(sc, BM_HASHTAB1, 0);  in bm_init_locked()
1151 	CSR_WRITE_2(sc, BM_HASHTAB2, 0);  in bm_init_locked()
1152 	CSR_WRITE_2(sc, BM_HASHTAB3, 0);  in bm_init_locked()
1155 	CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]);  in bm_init_locked()
1156 	CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]);  in bm_init_locked()
1157 	CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]);  in bm_init_locked()
1161 	CSR_WRITE_2(sc, BM_RX_CONFIG, reg);  in bm_init_locked()
1173 	CSR_WRITE_2(sc, BM_TX_CONFIG, reg);  in bm_init_locked()
1212 	CSR_WRITE_2(sc, BM_TX_NCCNT, 0);  in bm_tick()
1213 	CSR_WRITE_2(sc, BM_TX_FCCNT, 0);  in bm_tick()
1214 	CSR_WRITE_2(sc, BM_TX_EXCNT, 0);  in bm_tick()
1215 	CSR_WRITE_2(sc, BM_TX_LTCNT, 0);  in bm_tick()
1218 	CSR_WRITE_2(sc, BM_RX_FRCNT, 0);  in bm_tick()
1219 	CSR_WRITE_2(sc, BM_RX_LECNT, 0);  in bm_tick()
1220 	CSR_WRITE_2(sc, BM_RX_AECNT, 0);  in bm_tick()
1221 	CSR_WRITE_2(sc, BM_RX_FECNT, 0);  in bm_tick()
1222 	CSR_WRITE_2(sc, BM_RXCV, 0);  in bm_tick()
1292 	CSR_WRITE_2(sc, BM_INTR_DISABLE,  in bm_enable_interrupts()
1299 	CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE);  in bm_disable_interrupts()