Lines Matching refs:ProcModel
94 unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
96 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
98 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
102 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
104 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
107 const CodeGenProcModel &ProcModel);
109 const CodeGenProcModel &ProcModel);
111 const CodeGenProcModel &ProcModel);
112 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
362 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
364 if (!ItinsDefSet.insert(ProcModel.ItinsDef).second) in EmitStageAndOperandCycleData()
367 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
371 StringRef Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
381 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
415 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
422 if (!ProcModel.hasItineraries()) in EmitStageAndOperandCycleData()
425 StringRef Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
428 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); in EmitStageAndOperandCycleData()
434 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData()
597 const CodeGenProcModel &ProcModel, raw_ostream &OS) { in EmitProcessorResourceSubUnits() argument
598 OS << "\nstatic const unsigned " << ProcModel.ModelName in EmitProcessorResourceSubUnits()
602 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResourceSubUnits()
603 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResourceSubUnits()
609 SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc()); in EmitProcessorResourceSubUnits()
611 OS << " " << ProcModel.getProcResourceIdx(RU) << ", "; in EmitProcessorResourceSubUnits()
619 static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, in EmitRetireControlUnitInfo() argument
622 if (Record *RCU = ProcModel.RetireControlUnit) { in EmitRetireControlUnitInfo()
633 static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, in EmitRegisterFileInfo() argument
637 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles); in EmitRegisterFileInfo()
643 OS << ProcModel.ModelName << "RegisterCosts,\n "; in EmitRegisterFileInfo()
650 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, in EmitRegisterFileTables() argument
652 if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) { in EmitRegisterFileTables()
659 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName in EmitRegisterFileTables()
663 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
682 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName in EmitRegisterFileTables()
688 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
702 void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, in EmitLoadStoreQueueInfo() argument
705 if (ProcModel.LoadQueue) { in EmitLoadStoreQueueInfo()
706 const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor"); in EmitLoadStoreQueueInfo()
708 1 + std::distance(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
709 std::find(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
710 ProcModel.ProcResourceDefs.end(), Queue)); in EmitLoadStoreQueueInfo()
715 if (ProcModel.StoreQueue) { in EmitLoadStoreQueueInfo()
717 ProcModel.StoreQueue->getValueAsDef("QueueDescriptor"); in EmitLoadStoreQueueInfo()
719 1 + std::distance(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
720 std::find(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
721 ProcModel.ProcResourceDefs.end(), Queue)); in EmitLoadStoreQueueInfo()
726 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, in EmitExtraProcessorInfo() argument
730 unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS); in EmitExtraProcessorInfo()
733 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName in EmitExtraProcessorInfo()
737 EmitRetireControlUnitInfo(ProcModel, OS); in EmitExtraProcessorInfo()
741 EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), in EmitExtraProcessorInfo()
745 EmitLoadStoreQueueInfo(ProcModel, OS); in EmitExtraProcessorInfo()
750 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, in EmitProcessorResources() argument
752 EmitProcessorResourceSubUnits(ProcModel, OS); in EmitProcessorResources()
755 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName in EmitProcessorResources()
761 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResources()
762 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResources()
781 ProcModel, PRDef->getLoc()); in EmitProcessorResources()
782 SuperIdx = ProcModel.getProcResourceIdx(SuperDef); in EmitProcessorResources()
792 OS << ProcModel.ModelName << "ProcResourceSubUnits + " in EmitProcessorResources()
808 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
821 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
826 "defined for processor " + ProcModel.ModelName + in FindWriteResources()
835 for (Record *WR : ProcModel.WriteResDefs) { in FindWriteResources()
843 ProcModel.ModelName); in FindWriteResources()
851 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
861 const CodeGenProcModel &ProcModel) { in FindReadAdvance() argument
873 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
878 "defined for processor " + ProcModel.ModelName + in FindReadAdvance()
887 for (Record *RA : ProcModel.ReadAdvanceDefs) { in FindReadAdvance()
895 ProcModel.ModelName); in FindReadAdvance()
903 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
959 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, in GenSchedClassTables() argument
962 if (!ProcModel.hasInstrSchedModel()) in GenSchedClassTables()
985 is_contained(CGT.ProcIndices, ProcModel.Index)) { in GenSchedClassTables()
1000 if (!is_contained(SC.ProcIndices, ProcModel.Index)) in GenSchedClassTables()
1011 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) { in GenSchedClassTables()
1025 for (Record *I : ProcModel.ItinRWDefs) { in GenSchedClassTables()
1034 LLVM_DEBUG(dbgs() << ProcModel.ModelName in GenSchedClassTables()
1047 ProcModel); in GenSchedClassTables()
1065 FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel); in GenSchedClassTables()
1099 ExpandProcResources(PRVec, Cycles, ProcModel); in GenSchedClassTables()
1104 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]); in GenSchedClassTables()
1130 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1421 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitSchedModel() local
1422 GenSchedClassTables(ProcModel, SchedTables); in EmitSchedModel()