Lines Matching refs:OS
77 void Enumeration(raw_ostream &OS);
78 unsigned FeatureKeyValues(raw_ostream &OS);
79 unsigned CPUKeyValues(raw_ostream &OS);
88 void EmitStageAndOperandCycleData(raw_ostream &OS,
91 void EmitItineraries(raw_ostream &OS,
95 raw_ostream &OS);
97 raw_ostream &OS);
99 raw_ostream &OS);
100 void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
103 raw_ostream &OS);
105 raw_ostream &OS);
114 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
115 void EmitProcessorModels(raw_ostream &OS);
116 void EmitProcessorLookup(raw_ostream &OS);
117 void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
118 void emitSchedModelHelpersImpl(raw_ostream &OS,
120 void emitGenMCSubtargetInfo(raw_ostream &OS);
121 void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS);
123 void EmitSchedModel(raw_ostream &OS);
124 void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
125 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
141 void SubtargetEmitter::Enumeration(raw_ostream &OS) { in Enumeration() argument
153 OS << "namespace " << Target << " {\n"; in Enumeration()
156 OS << "enum {\n"; in Enumeration()
164 OS << " " << Def->getName() << " = " << i << ",\n"; in Enumeration()
168 OS << "};\n"; in Enumeration()
169 OS << "} // end namespace " << Target << "\n"; in Enumeration()
176 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { in FeatureKeyValues() argument
187 OS << "// Sorted (by key) array of values for CPU features.\n" in FeatureKeyValues()
204 OS << " { " in FeatureKeyValues()
211 OS << "{"; in FeatureKeyValues()
213 OS << " " << Target << "::" << ImpliesList[j]->getName(); in FeatureKeyValues()
214 if (++j < M) OS << ","; in FeatureKeyValues()
216 OS << " } },\n"; in FeatureKeyValues()
221 OS << "};\n"; in FeatureKeyValues()
230 unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { in CPUKeyValues() argument
237 OS << "// Sorted (by key) array of values for CPU subtype.\n" in CPUKeyValues()
247 OS << " { " in CPUKeyValues()
251 OS << "{"; in CPUKeyValues()
253 OS << " " << Target << "::" << FeatureList[j]->getName(); in CPUKeyValues()
254 if (++j < M) OS << ","; in CPUKeyValues()
257 OS << " }, { } },\n"; in CPUKeyValues()
261 OS << "};\n"; in CPUKeyValues()
355 EmitStageAndOperandCycleData(raw_ostream &OS, in EmitStageAndOperandCycleData() argument
372 OS << "\n// Functional units for \"" << Name << "\"\n" in EmitStageAndOperandCycleData()
376 OS << " const unsigned " << FUs[j]->getName() in EmitStageAndOperandCycleData()
379 OS << "} // end namespace " << Name << "FU\n"; in EmitStageAndOperandCycleData()
383 OS << "\n// Pipeline forwarding paths for itineraries \"" << Name in EmitStageAndOperandCycleData()
386 OS << " const unsigned NoBypass = 0;\n"; in EmitStageAndOperandCycleData()
388 OS << " const unsigned " << BPs[j]->getName() in EmitStageAndOperandCycleData()
391 OS << "} // end namespace " << Name << "Bypass\n"; in EmitStageAndOperandCycleData()
519 OS << StageTable; in EmitStageAndOperandCycleData()
520 OS << OperandCycleTable; in EmitStageAndOperandCycleData()
521 OS << BypassTable; in EmitStageAndOperandCycleData()
531 EmitItineraries(raw_ostream &OS, in EmitItineraries() argument
555 OS << "\n"; in EmitItineraries()
556 OS << "static const llvm::InstrItinerary "; in EmitItineraries()
559 OS << ItinsDef->getName() << "[] = {\n"; in EmitItineraries()
567 OS << " { " << in EmitItineraries()
576 OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }" in EmitItineraries()
578 OS << "};\n"; in EmitItineraries()
585 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R, in EmitProcessorProp() argument
587 OS << " "; in EmitProcessorProp()
590 OS << V << Separator << " // " << Name; in EmitProcessorProp()
592 OS << "MCSchedModel::Default" << Name << Separator; in EmitProcessorProp()
593 OS << '\n'; in EmitProcessorProp()
597 const CodeGenProcModel &ProcModel, raw_ostream &OS) { in EmitProcessorResourceSubUnits() argument
598 OS << "\nstatic const unsigned " << ProcModel.ModelName in EmitProcessorResourceSubUnits()
611 OS << " " << ProcModel.getProcResourceIdx(RU) << ", "; in EmitProcessorResourceSubUnits()
614 OS << " // " << PRDef->getName() << "\n"; in EmitProcessorResourceSubUnits()
616 OS << "};\n"; in EmitProcessorResourceSubUnits()
620 raw_ostream &OS) { in EmitRetireControlUnitInfo() argument
629 OS << ReorderBufferSize << ", // ReorderBufferSize\n "; in EmitRetireControlUnitInfo()
630 OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n "; in EmitRetireControlUnitInfo()
635 unsigned NumCostEntries, raw_ostream &OS) { in EmitRegisterFileInfo() argument
637 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles); in EmitRegisterFileInfo()
639 OS << "nullptr,\n 0"; in EmitRegisterFileInfo()
641 OS << ", // Number of register files.\n "; in EmitRegisterFileInfo()
643 OS << ProcModel.ModelName << "RegisterCosts,\n "; in EmitRegisterFileInfo()
645 OS << "nullptr,\n "; in EmitRegisterFileInfo()
646 OS << NumCostEntries << ", // Number of register cost entries.\n"; in EmitRegisterFileInfo()
651 raw_ostream &OS) { in EmitRegisterFileTables() argument
658 OS << "\n// {RegisterClassID, Register Cost, AllowMoveElimination }\n"; in EmitRegisterFileTables()
659 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName in EmitRegisterFileTables()
669 OS << " { "; in EmitRegisterFileTables()
672 OS << Rec->getValueAsString("Namespace") << "::"; in EmitRegisterFileTables()
673 OS << Rec->getName() << "RegClassID, " << RC.Cost << ", " in EmitRegisterFileTables()
677 OS << "};\n"; in EmitRegisterFileTables()
680 OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl, " in EmitRegisterFileTables()
682 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName in EmitRegisterFileTables()
689 OS << " { "; in EmitRegisterFileTables()
690 OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", "; in EmitRegisterFileTables()
692 OS << NumCostEntries << ", " << CostTblIndex << ", " in EmitRegisterFileTables()
697 OS << "};\n"; in EmitRegisterFileTables()
703 raw_ostream &OS) { in EmitLoadStoreQueueInfo() argument
712 OS << " " << QueueID << ", // Resource Descriptor for the Load Queue\n"; in EmitLoadStoreQueueInfo()
723 OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n"; in EmitLoadStoreQueueInfo()
727 raw_ostream &OS) { in EmitExtraProcessorInfo() argument
730 unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS); in EmitExtraProcessorInfo()
733 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName in EmitExtraProcessorInfo()
737 EmitRetireControlUnitInfo(ProcModel, OS); in EmitExtraProcessorInfo()
742 NumCostEntries, OS); in EmitExtraProcessorInfo()
745 EmitLoadStoreQueueInfo(ProcModel, OS); in EmitExtraProcessorInfo()
747 OS << "};\n"; in EmitExtraProcessorInfo()
751 raw_ostream &OS) { in EmitProcessorResources() argument
752 EmitProcessorResourceSubUnits(ProcModel, OS); in EmitProcessorResources()
754 OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n"; in EmitProcessorResources()
755 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName in EmitProcessorResources()
787 OS << " {\"" << PRDef->getName() << "\", "; in EmitProcessorResources()
789 OS.indent(15 - PRDef->getName().size()); in EmitProcessorResources()
790 OS << NumUnits << ", " << SuperIdx << ", " << BufferSize << ", "; in EmitProcessorResources()
792 OS << ProcModel.ModelName << "ProcResourceSubUnits + " in EmitProcessorResources()
795 OS << "nullptr"; in EmitProcessorResources()
797 OS << "}, // #" << i+1; in EmitProcessorResources()
799 OS << ", Super=" << SuperDef->getName(); in EmitProcessorResources()
800 OS << "\n"; in EmitProcessorResources()
802 OS << "};\n"; in EmitProcessorResources()
1221 raw_ostream &OS) { in EmitSchedClassTables() argument
1223 OS << "\n// {ProcResourceIdx, Cycles}\n" in EmitSchedClassTables()
1230 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", " in EmitSchedClassTables()
1233 OS << ','; in EmitSchedClassTables()
1234 OS << " // #" << WPRIdx << '\n'; in EmitSchedClassTables()
1236 OS << "}; // " << Target << "WriteProcResTable\n"; in EmitSchedClassTables()
1239 OS << "\n// {Cycles, WriteResourceID}\n" in EmitSchedClassTables()
1246 OS << " {" << format("%2d", WLEntry.Cycles) << ", " in EmitSchedClassTables()
1249 OS << ','; in EmitSchedClassTables()
1250 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n'; in EmitSchedClassTables()
1252 OS << "}; // " << Target << "WriteLatencyTable\n"; in EmitSchedClassTables()
1255 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n" in EmitSchedClassTables()
1262 OS << " {" << RAEntry.UseIdx << ", " in EmitSchedClassTables()
1266 OS << ','; in EmitSchedClassTables()
1267 OS << " // #" << RAIdx << '\n'; in EmitSchedClassTables()
1269 OS << "}; // " << Target << "ReadAdvanceTable\n"; in EmitSchedClassTables()
1280 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup," in EmitSchedClassTables()
1282 OS << "static const llvm::MCSchedClassDesc " in EmitSchedClassTables()
1289 OS << " {DBGFIELD(\"InvalidSchedClass\") " in EmitSchedClassTables()
1296 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") "; in EmitSchedClassTables()
1298 OS.indent(18 - SchedClass.Name.size()); in EmitSchedClassTables()
1299 OS << MCDesc.NumMicroOps in EmitSchedClassTables()
1310 OS << "}; // " << PI->ModelName << "SchedClasses\n"; in EmitSchedClassTables()
1314 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { in EmitProcessorModels() argument
1319 EmitExtraProcessorInfo(PM, OS); in EmitProcessorModels()
1322 EmitProcessorResources(PM, OS); in EmitProcessorModels()
1328 OS << "\n"; in EmitProcessorModels()
1329 OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n"; in EmitProcessorModels()
1330 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); in EmitProcessorModels()
1331 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); in EmitProcessorModels()
1332 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); in EmitProcessorModels()
1333 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); in EmitProcessorModels()
1334 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); in EmitProcessorModels()
1335 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); in EmitProcessorModels()
1340 OS << " " << (PostRAScheduler ? "true" : "false") << ", // " in EmitProcessorModels()
1346 OS << " " << (CompleteModel ? "true" : "false") << ", // " in EmitProcessorModels()
1349 OS << " " << PM.Index << ", // Processor ID\n"; in EmitProcessorModels()
1351 OS << " " << PM.ModelName << "ProcResources" << ",\n" in EmitProcessorModels()
1357 OS << " nullptr, nullptr, 0, 0," in EmitProcessorModels()
1360 OS << " " << PM.ItinsDef->getName() << ",\n"; in EmitProcessorModels()
1362 OS << " nullptr, // No Itinerary\n"; in EmitProcessorModels()
1364 OS << " &" << PM.ModelName << "ExtraInfo,\n"; in EmitProcessorModels()
1366 OS << " nullptr // No extra processor descriptor\n"; in EmitProcessorModels()
1367 OS << "};\n"; in EmitProcessorModels()
1374 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { in EmitProcessorLookup() argument
1381 OS << "\n"; in EmitProcessorLookup()
1382 OS << "// Sorted (by key) array of sched model for CPU subtype.\n" in EmitProcessorLookup()
1392 OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " },\n"; in EmitProcessorLookup()
1395 OS << "};\n"; in EmitProcessorLookup()
1401 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { in EmitSchedModel() argument
1402 OS << "#ifdef DBGFIELD\n" in EmitSchedModel()
1414 EmitStageAndOperandCycleData(OS, ProcItinLists); in EmitSchedModel()
1415 EmitItineraries(OS, ProcItinLists); in EmitSchedModel()
1417 OS << "\n// ===============================================================\n" in EmitSchedModel()
1424 EmitSchedClassTables(SchedTables, OS); in EmitSchedModel()
1427 EmitProcessorModels(OS); in EmitSchedModel()
1429 EmitProcessorLookup(OS); in EmitSchedModel()
1431 OS << "\n#undef DBGFIELD"; in EmitSchedModel()
1434 static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) { in emitPredicateProlog() argument
1447 OS << Buffer; in emitPredicateProlog()
1452 raw_ostream &OS) { in emitPredicates() argument
1506 OS << Buffer; in emitPredicates()
1511 void emitSchedModelHelperEpilogue(raw_ostream &OS, bool ShouldReturnZero) { in emitSchedModelHelperEpilogue() argument
1513 OS << " // Don't know how to resolve this scheduling class.\n" in emitSchedModelHelperEpilogue()
1518 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n"; in emitSchedModelHelperEpilogue()
1562 raw_ostream &OS, bool OnlyExpandMCInstPredicates) { in emitSchedModelHelpersImpl() argument
1568 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates); in emitSchedModelHelpersImpl()
1579 OS << " switch (SchedClass) {\n"; in emitSchedModelHelpersImpl()
1585 OS << " case " << VC << ": // " << SC.Name << '\n'; in emitSchedModelHelpersImpl()
1591 OS << " "; in emitSchedModelHelpersImpl()
1595 OS << (OnlyExpandMCInstPredicates in emitSchedModelHelpersImpl()
1598 OS << PI << ") "; in emitSchedModelHelpersImpl()
1599 OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName << '\n'; in emitSchedModelHelpersImpl()
1618 emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS); in emitSchedModelHelpersImpl()
1621 OS << " }\n"; in emitSchedModelHelpersImpl()
1628 OS << " return " << SC.Index << ";\n"; in emitSchedModelHelpersImpl()
1629 OS << " break;\n"; in emitSchedModelHelpersImpl()
1632 OS << " };\n"; in emitSchedModelHelpersImpl()
1634 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates); in emitSchedModelHelpersImpl()
1638 raw_ostream &OS) { in EmitSchedModelHelpers() argument
1639 OS << "unsigned " << ClassName in EmitSchedModelHelpers()
1644 emitPredicateProlog(Records, OS); in EmitSchedModelHelpers()
1647 emitSchedModelHelpersImpl(OS); in EmitSchedModelHelpers()
1649 OS << "} // " << ClassName << "::resolveSchedClass\n\n"; in EmitSchedModelHelpers()
1651 OS << "unsigned " << ClassName in EmitSchedModelHelpers()
1665 PE.expandSTIPredicate(OS, Fn); in EmitSchedModelHelpers()
1669 raw_ostream &OS) { in EmitHwModeCheck() argument
1675 OS << "unsigned " << ClassName << "::getHwMode() const {\n"; in EmitHwModeCheck()
1678 OS << " if (checkFeatures(\"" << HM.Features in EmitHwModeCheck()
1681 OS << " return 0;\n}\n"; in EmitHwModeCheck()
1688 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS, in ParseFeaturesFunction() argument
1695 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" in ParseFeaturesFunction()
1698 OS << Target; in ParseFeaturesFunction()
1699 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n" in ParseFeaturesFunction()
1704 OS << "}\n"; in ParseFeaturesFunction()
1708 OS << " InitMCProcessorInfo(CPU, FS);\n" in ParseFeaturesFunction()
1718 OS << " if (Bits[" << Target << "::" in ParseFeaturesFunction()
1722 OS << " if (Bits[" << Target << "::" in ParseFeaturesFunction()
1728 OS << "}\n"; in ParseFeaturesFunction()
1731 void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { in emitGenMCSubtargetInfo() argument
1732 OS << "namespace " << Target << "_MC {\n" in emitGenMCSubtargetInfo()
1735 emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true); in emitGenMCSubtargetInfo()
1736 OS << "}\n"; in emitGenMCSubtargetInfo()
1737 OS << "} // end of namespace " << Target << "_MC\n\n"; in emitGenMCSubtargetInfo()
1739 OS << "struct " << Target in emitGenMCSubtargetInfo()
1741 OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT, \n" in emitGenMCSubtargetInfo()
1755 OS << " }\n"; in emitGenMCSubtargetInfo()
1756 OS << "};\n"; in emitGenMCSubtargetInfo()
1759 void SubtargetEmitter::EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS) { in EmitMCInstrAnalysisPredicateFunctions() argument
1760 OS << "\n#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n"; in EmitMCInstrAnalysisPredicateFunctions()
1761 OS << "#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n"; in EmitMCInstrAnalysisPredicateFunctions()
1767 PE.expandSTIPredicate(OS, Fn); in EmitMCInstrAnalysisPredicateFunctions()
1769 OS << "#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n"; in EmitMCInstrAnalysisPredicateFunctions()
1771 OS << "\n#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n"; in EmitMCInstrAnalysisPredicateFunctions()
1772 OS << "#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n\n"; in EmitMCInstrAnalysisPredicateFunctions()
1779 PE.expandSTIPredicate(OS, Fn); in EmitMCInstrAnalysisPredicateFunctions()
1781 OS << "#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n\n"; in EmitMCInstrAnalysisPredicateFunctions()
1787 void SubtargetEmitter::run(raw_ostream &OS) { in run() argument
1788 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); in run()
1790 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; in run()
1791 OS << "#undef GET_SUBTARGETINFO_ENUM\n\n"; in run()
1793 OS << "namespace llvm {\n"; in run()
1794 Enumeration(OS); in run()
1795 OS << "} // end namespace llvm\n\n"; in run()
1796 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; in run()
1798 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; in run()
1799 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n"; in run()
1801 OS << "namespace llvm {\n"; in run()
1803 OS << "namespace {\n"; in run()
1805 unsigned NumFeatures = FeatureKeyValues(OS); in run()
1806 OS << "\n"; in run()
1807 unsigned NumProcs = CPUKeyValues(OS); in run()
1808 OS << "\n"; in run()
1809 EmitSchedModel(OS); in run()
1810 OS << "\n"; in run()
1812 OS << "} // end anonymous namespace\n\n"; in run()
1816 emitGenMCSubtargetInfo(OS); in run()
1818 OS << "\nstatic inline MCSubtargetInfo *create" << Target in run()
1821 OS << " return new " << Target << "GenMCSubtargetInfo(TT, CPU, FS, "; in run()
1823 OS << Target << "FeatureKV, "; in run()
1825 OS << "None, "; in run()
1827 OS << Target << "SubTypeKV, "; in run()
1829 OS << "None, "; in run()
1830 OS << '\n'; OS.indent(22); in run()
1831 OS << Target << "ProcSchedKV, " in run()
1835 OS << '\n'; OS.indent(22); in run()
1837 OS << Target << "Stages, " in run()
1841 OS << "nullptr, nullptr, nullptr"; in run()
1842 OS << ");\n}\n\n"; in run()
1844 OS << "} // end namespace llvm\n\n"; in run()
1846 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n"; in run()
1848 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n"; in run()
1849 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n"; in run()
1851 OS << "#include \"llvm/Support/Debug.h\"\n"; in run()
1852 OS << "#include \"llvm/Support/raw_ostream.h\"\n\n"; in run()
1853 ParseFeaturesFunction(OS, NumFeatures, NumProcs); in run()
1855 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n"; in run()
1858 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n"; in run()
1859 OS << "#undef GET_SUBTARGETINFO_HEADER\n\n"; in run()
1862 OS << "namespace llvm {\n"; in run()
1863 OS << "class DFAPacketizer;\n"; in run()
1864 OS << "namespace " << Target << "_MC {\n" in run()
1868 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n" in run()
1880 OS << " unsigned getHwMode() const override;\n"; in run()
1885 PE.expandSTIPredicate(OS, Fn); in run()
1887 OS << "};\n" in run()
1890 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n"; in run()
1892 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n"; in run()
1893 OS << "#undef GET_SUBTARGETINFO_CTOR\n\n"; in run()
1895 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n"; in run()
1896 OS << "namespace llvm {\n"; in run()
1897 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n"; in run()
1898 OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n"; in run()
1899 OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n"; in run()
1900 OS << "extern const llvm::MCWriteProcResEntry " in run()
1902 OS << "extern const llvm::MCWriteLatencyEntry " in run()
1904 OS << "extern const llvm::MCReadAdvanceEntry " in run()
1908 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n"; in run()
1909 OS << "extern const unsigned " << Target << "OperandCycles[];\n"; in run()
1910 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n"; in run()
1913 OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, " in run()
1917 OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), "; in run()
1919 OS << "None, "; in run()
1921 OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), "; in run()
1923 OS << "None, "; in run()
1924 OS << '\n'; OS.indent(24); in run()
1925 OS << Target << "ProcSchedKV, " in run()
1929 OS << '\n'; OS.indent(24); in run()
1931 OS << Target << "Stages, " in run()
1935 OS << "nullptr, nullptr, nullptr"; in run()
1936 OS << ") {}\n\n"; in run()
1938 EmitSchedModelHelpers(ClassName, OS); in run()
1939 EmitHwModeCheck(ClassName, OS); in run()
1941 OS << "} // end namespace llvm\n\n"; in run()
1943 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; in run()
1945 EmitMCInstrAnalysisPredicateFunctions(OS); in run()
1950 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) { in EmitSubtarget() argument
1952 SubtargetEmitter(RK, CGTarget).run(OS); in EmitSubtarget()