Lines Matching refs:ModelDef
820 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindWriteResources() local
821 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
851 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
872 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindReadAdvance() local
873 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
903 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
1324 PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines " in EmitProcessorModels()
1330 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); in EmitProcessorModels()
1331 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); in EmitProcessorModels()
1332 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); in EmitProcessorModels()
1333 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); in EmitProcessorModels()
1334 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); in EmitProcessorModels()
1335 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); in EmitProcessorModels()
1338 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); in EmitProcessorModels()
1344 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false); in EmitProcessorModels()