Lines Matching refs:Cycles
110 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
285 int Cycles = Stage->getValueAsInt("Cycles"); in FormItineraryStageString() local
286 ItinString += " { " + itostr(Cycles) + ", "; in FormItineraryStageString()
913 std::vector<int64_t> &Cycles, in ExpandProcResources() argument
915 assert(PRVec.size() == Cycles.size() && "failed precondition"); in ExpandProcResources()
935 Cycles.push_back(Cycles[i]); in ExpandProcResources()
951 Cycles.push_back(Cycles[i]); in ExpandProcResources()
1051 WLEntry.Cycles = 0; in GenSchedClassTables()
1072 WLEntry.Cycles += WriteRes->getValueAsInt("Latency"); in GenSchedClassTables()
1081 std::vector<int64_t> Cycles = in GenSchedClassTables() local
1084 if (Cycles.empty()) { in GenSchedClassTables()
1087 Cycles.resize(PRVec.size(), 1); in GenSchedClassTables()
1088 } else if (Cycles.size() != PRVec.size()) { in GenSchedClassTables()
1096 .concat(Twine(Cycles.size()))); in GenSchedClassTables()
1099 ExpandProcResources(PRVec, Cycles, ProcModel); in GenSchedClassTables()
1106 WPREntry.Cycles = Cycles[PRIdx]; in GenSchedClassTables()
1115 WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles; in GenSchedClassTables()
1153 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles"); in GenSchedClassTables()
1231 << format("%2d", WPREntry.Cycles) << "}"; in EmitSchedClassTables()
1246 OS << " {" << format("%2d", WLEntry.Cycles) << ", " in EmitSchedClassTables()
1264 << format("%2d", RAEntry.Cycles) << "}"; in EmitSchedClassTables()