Lines Matching refs:getName
120 << "extern const MCRegisterClass " << Target.getName() in runEnums()
128 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
148 OS << " " << RC.getName() << "RegClassID" in runEnums()
164 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
180 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
214 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
357 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) in finalizeDwarfRegNumsKeys()
366 return A.first->getName() == B.first->getName(); in finalizeDwarfRegNumsKeys()
822 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
901 RegStrings.add(Reg.getName()); in runMCDesc()
967 const std::string &TargetName = Target.getName(); in runMCDesc()
990 << Idx.getName() << "\n"; in runMCDesc()
1007 OS << " { " << RegStrings.get(Reg.getName()) << ", " in runMCDesc()
1042 const std::string &Name = RC.getName(); in runMCDesc()
1078 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1079 << RegClassStrings.get(RC.getName()) << ", " in runMCDesc()
1080 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " in runMCDesc()
1138 const std::string &TargetName = Target.getName(); in runTargetHeader()
1186 const std::string &Name = RC.getName(); in runTargetHeader()
1211 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1251 OS << Idx.getName(); in runTargetDesc()
1261 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1289 << RC.getName() << '\n'; in runTargetDesc()
1323 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1338 OS << "// " << Idx.getName(); in runTargetDesc()
1358 << RC.getName() << "Superclasses[] = {\n"; in runTargetDesc()
1367 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1370 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1381 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1390 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1401 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1402 << "RegClass = {\n " << '&' << Target.getName() in runTargetDesc()
1403 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " in runTargetDesc()
1404 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " in runTargetDesc()
1415 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1419 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1434 const std::string &TargetName = Target.getName(); in runTargetDesc()
1449 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; in runTargetDesc()
1474 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1477 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1478 << " -> " << SRC->getName() << "\n"; in runTargetDesc()
1480 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1543 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1562 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1574 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1587 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1627 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1640 OS << " " << R->getName(); in debugDump()
1648 OS << " " << SRC.getName(); in debugDump()
1653 OS << " " << SRC->getName(); in debugDump()
1659 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1665 OS << "Register " << R.getName() << ":\n"; in debugDump()
1670 OS << "\tSubReg " << P.first->getName() in debugDump()
1671 << " = " << P.second->getName() << '\n'; in debugDump()