Lines Matching refs:OS
84 void debugDump(raw_ostream &OS);
92 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
94 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
96 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
103 void RegisterInfoEmitter::runEnums(raw_ostream &OS, in runEnums() argument
112 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
114 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
115 OS << "#undef GET_REGINFO_ENUM\n\n"; in runEnums()
117 OS << "namespace llvm {\n\n"; in runEnums()
119 OS << "class MCRegisterClass;\n" in runEnums()
124 OS << "namespace " << Namespace << " {\n"; in runEnums()
125 OS << "enum {\n NoRegister,\n"; in runEnums()
128 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
131 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; in runEnums()
132 OS << "};\n"; in runEnums()
134 OS << "} // end namespace " << Namespace << "\n"; in runEnums()
143 OS << "\n// Register classes\n\n"; in runEnums()
145 OS << "namespace " << Namespace << " {\n"; in runEnums()
146 OS << "enum {\n"; in runEnums()
148 OS << " " << RC.getName() << "RegClassID" in runEnums()
150 OS << "\n };\n"; in runEnums()
152 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
159 OS << "\n// Register alternate name indices\n\n"; in runEnums()
161 OS << "namespace " << Namespace << " {\n"; in runEnums()
162 OS << "enum {\n"; in runEnums()
164 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
165 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
166 OS << "};\n"; in runEnums()
168 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
173 OS << "\n// Subregister indices\n\n"; in runEnums()
176 OS << "namespace " << Namespace << " {\n"; in runEnums()
177 OS << "enum {\n NoSubRegister,\n"; in runEnums()
180 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
181 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
183 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
186 OS << "} // end namespace llvm\n\n"; in runEnums()
187 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
190 static void printInt(raw_ostream &OS, int Val) { in printInt() argument
191 OS << Val; in printInt()
195 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
200 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
207 OS << " {0, 0"; in EmitRegUnitPressure()
211 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
214 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
216 OS << " };\n" in EmitRegUnitPressure()
228 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
234 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
239 OS << RU.Weight << ", "; in EmitRegUnitPressure()
241 OS << "};\n" in EmitRegUnitPressure()
245 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
248 OS << "}\n\n"; in EmitRegUnitPressure()
250 OS << "\n" in EmitRegUnitPressure()
255 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
263 OS << " \"" << RegUnits.Name << "\",\n"; in EmitRegUnitPressure()
265 OS << " };\n" in EmitRegUnitPressure()
269 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
278 OS << " " << RegUnits.Weight << ", \t// " << i << ": " in EmitRegUnitPressure()
281 OS << " };\n" in EmitRegUnitPressure()
305 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
307 PSetsSeqs.emit(OS, printInt, "-1"); in EmitRegUnitPressure()
308 OS << "};\n\n"; in EmitRegUnitPressure()
310 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
315 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
318 OS << PSetsSeqs.get(PSets[i]) << ","; in EmitRegUnitPressure()
320 OS << "};\n" in EmitRegUnitPressure()
324 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
331 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
335 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) in EmitRegUnitPressure()
338 OS << "};\n" in EmitRegUnitPressure()
372 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
398 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
403 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
404 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
405 OS << i << "Dwarf2L[]"; in EmitRegMappingTables()
408 OS << " = {\n"; in EmitRegMappingTables()
423 OS << " { " << I->first << "U, " << getQualifiedName(I->second) in EmitRegMappingTables()
426 OS << "};\n"; in EmitRegMappingTables()
428 OS << ";\n"; in EmitRegMappingTables()
433 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
436 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
440 OS << ";\n\n"; in EmitRegMappingTables()
472 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
473 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
474 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
476 OS << " = {\n"; in EmitRegMappingTables()
485 OS << " { " << getQualifiedName(I->first) << ", " << RegNo in EmitRegMappingTables()
488 OS << "};\n"; in EmitRegMappingTables()
490 OS << ";\n"; in EmitRegMappingTables()
495 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
498 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
501 OS << ";\n\n"; in EmitRegMappingTables()
507 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
524 OS << " switch ("; in EmitRegMapping()
526 OS << "DwarfFlavour"; in EmitRegMapping()
528 OS << "EHFlavour"; in EmitRegMapping()
529 OS << ") {\n" in EmitRegMapping()
534 OS << " case " << i << ":\n"; in EmitRegMapping()
535 OS << " "; in EmitRegMapping()
537 OS << "RI->"; in EmitRegMapping()
542 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
544 OS << "false"; in EmitRegMapping()
546 OS << "true"; in EmitRegMapping()
547 OS << ");\n"; in EmitRegMapping()
548 OS << " break;\n"; in EmitRegMapping()
550 OS << " }\n"; in EmitRegMapping()
555 OS << " switch ("; in EmitRegMapping()
557 OS << "DwarfFlavour"; in EmitRegMapping()
559 OS << "EHFlavour"; in EmitRegMapping()
560 OS << ") {\n" in EmitRegMapping()
565 OS << " case " << i << ":\n"; in EmitRegMapping()
566 OS << " "; in EmitRegMapping()
568 OS << "RI->"; in EmitRegMapping()
573 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
575 OS << "false"; in EmitRegMapping()
577 OS << "true"; in EmitRegMapping()
578 OS << ");\n"; in EmitRegMapping()
579 OS << " break;\n"; in EmitRegMapping()
581 OS << " }\n"; in EmitRegMapping()
587 static void printBitVectorAsHex(raw_ostream &OS, in printBitVectorAsHex() argument
596 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
610 void print(raw_ostream &OS) { in print() argument
611 printBitVectorAsHex(OS, Values, 8); in print()
615 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
616 OS << getEnumName(VT); in printSimpleValueType()
619 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
620 OS << Idx->EnumValue; in printSubRegIndex()
663 static void printDiff16(raw_ostream &OS, uint16_t Val) { in printDiff16() argument
664 OS << Val; in printDiff16()
667 static void printMask(raw_ostream &OS, LaneBitmask Val) { in printMask() argument
668 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; in printMask()
693 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
697 OS << "unsigned " << ClName in emitComposeSubRegIndices()
732 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) in emitComposeSubRegIndices()
735 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
736 OS << "\n };\n"; in emitComposeSubRegIndices()
740 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) in emitComposeSubRegIndices()
743 OS << " { "; in emitComposeSubRegIndices()
746 OS << Rows[r][i]->EnumValue << ", "; in emitComposeSubRegIndices()
748 OS << "0, "; in emitComposeSubRegIndices()
749 OS << "},\n"; in emitComposeSubRegIndices()
751 OS << " };\n\n"; in emitComposeSubRegIndices()
753 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" in emitComposeSubRegIndices()
756 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
758 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
759 OS << "}\n\n"; in emitComposeSubRegIndices()
763 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, in emitComposeSubRegIndexLaneMask() argument
794 OS << " struct MaskRolOp {\n" in emitComposeSubRegIndexLaneMask()
801 OS << " "; in emitComposeSubRegIndexLaneMask()
805 printMask(OS << "{ ", P.Mask); in emitComposeSubRegIndexLaneMask()
806 OS << format(", %2u }, ", P.RotateLeft); in emitComposeSubRegIndexLaneMask()
808 OS << "{ LaneBitmask::getNone(), 0 }"; in emitComposeSubRegIndexLaneMask()
810 OS << ", "; in emitComposeSubRegIndexLaneMask()
811 OS << " // Sequence " << Idx << "\n"; in emitComposeSubRegIndexLaneMask()
814 OS << " };\n" in emitComposeSubRegIndexLaneMask()
817 OS << " "; in emitComposeSubRegIndexLaneMask()
819 OS << format("&LaneMaskComposeSequences[%u]", Idx); in emitComposeSubRegIndexLaneMask()
821 OS << ","; in emitComposeSubRegIndexLaneMask()
822 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
824 OS << " };\n\n"; in emitComposeSubRegIndexLaneMask()
826 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
842 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
864 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
866 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
868 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
869 OS << "#undef GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
965 OS << "namespace llvm {\n\n"; in runMCDesc()
970 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
971 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
972 OS << "};\n\n"; in runMCDesc()
975 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; in runMCDesc()
976 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); in runMCDesc()
977 OS << "};\n\n"; in runMCDesc()
980 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
981 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
982 OS << "};\n\n"; in runMCDesc()
985 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runMCDesc()
987 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runMCDesc()
989 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " in runMCDesc()
992 OS << "};\n\n"; in runMCDesc()
996 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; in runMCDesc()
997 RegStrings.emit(OS, printChar); in runMCDesc()
998 OS << "};\n\n"; in runMCDesc()
1000 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
1002 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; in runMCDesc()
1007 OS << " { " << RegStrings.get(Reg.getName()) << ", " in runMCDesc()
1014 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
1018 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
1023 OS << " { " << getQualifiedName(Roots.front()->TheDef); in runMCDesc()
1025 OS << ", " << getQualifiedName(Roots[r]->TheDef); in runMCDesc()
1026 OS << " },\n"; in runMCDesc()
1028 OS << "};\n\n"; in runMCDesc()
1033 OS << "namespace { // Register classes...\n"; in runMCDesc()
1047 OS << " // " << Name << " Register Class...\n" in runMCDesc()
1051 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
1053 OS << "\n };\n\n"; in runMCDesc()
1055 OS << " // " << Name << " Bit set.\n" in runMCDesc()
1062 BVE.print(OS); in runMCDesc()
1063 OS << "\n };\n\n"; in runMCDesc()
1066 OS << "} // end anonymous namespace\n\n"; in runMCDesc()
1069 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; in runMCDesc()
1070 RegClassStrings.emit(OS, printChar); in runMCDesc()
1071 OS << "};\n\n"; in runMCDesc()
1073 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
1078 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1086 OS << "};\n\n"; in runMCDesc()
1088 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1091 OS << "extern const uint16_t " << TargetName; in runMCDesc()
1092 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
1094 OS << " 0,\n"; in runMCDesc()
1103 OS << " " << Value << ",\n"; in runMCDesc()
1105 OS << "};\n"; // End of HW encoding table in runMCDesc()
1108 OS << "static inline void Init" << TargetName in runMCDesc()
1122 EmitRegMapping(OS, Regs, false); in runMCDesc()
1124 OS << "}\n\n"; in runMCDesc()
1126 OS << "} // end namespace llvm\n\n"; in runMCDesc()
1127 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
1131 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, in runTargetHeader() argument
1133 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
1135 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
1136 OS << "#undef GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1141 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
1143 OS << "namespace llvm {\n\n"; in runTargetHeader()
1145 OS << "class " << TargetName << "FrameLowering;\n\n"; in runTargetHeader()
1147 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
1152 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
1161 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
1182 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1189 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1191 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; in runTargetHeader()
1193 OS << "} // end namespace llvm\n\n"; in runTargetHeader()
1194 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1201 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
1203 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1205 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1206 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1208 OS << "namespace llvm {\n\n"; in runTargetDesc()
1211 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1243 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1244 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); in runTargetDesc()
1245 OS << "};\n"; in runTargetDesc()
1248 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; in runTargetDesc()
1251 OS << Idx.getName(); in runTargetDesc()
1252 OS << "\", \""; in runTargetDesc()
1254 OS << "\" };\n\n"; in runTargetDesc()
1257 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " in runTargetDesc()
1260 printMask(OS << " ", Idx.LaneMask); in runTargetDesc()
1261 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1263 OS << " };\n\n"; in runTargetDesc()
1265 OS << "\n"; in runTargetDesc()
1269 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" in runTargetDesc()
1273 OS << " // Mode = " << M << " ("; in runTargetDesc()
1275 OS << "Default"; in runTargetDesc()
1277 OS << CGH.getMode(M).Name; in runTargetDesc()
1278 OS << ")\n"; in runTargetDesc()
1283 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1288 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " in runTargetDesc()
1292 OS << "};\n"; in runTargetDesc()
1295 OS << "\nstatic const TargetRegisterClass *const " in runTargetDesc()
1323 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1325 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1336 OS << "\n "; in runTargetDesc()
1337 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1338 OS << "// " << Idx.getName(); in runTargetDesc()
1341 OS << "\n};\n\n"; in runTargetDesc()
1344 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1346 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1347 OS << "};\n\n"; in runTargetDesc()
1357 OS << "static const TargetRegisterClass *const " in runTargetDesc()
1360 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1361 OS << " nullptr\n};\n\n"; in runTargetDesc()
1367 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1375 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1377 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1378 OS << " };\n"; in runTargetDesc()
1381 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1387 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1389 OS << "),\n makeArrayRef(AltOrder" << oi; in runTargetDesc()
1390 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1397 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1401 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1406 printMask(OS, RC.LaneMask); in runTargetDesc()
1407 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1413 OS << "NullRegClasses,\n "; in runTargetDesc()
1415 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1417 OS << "nullptr\n"; in runTargetDesc()
1419 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1420 OS << " };\n\n"; in runTargetDesc()
1423 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; in runTargetDesc()
1426 OS << "\nnamespace {\n"; in runTargetDesc()
1427 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; in runTargetDesc()
1429 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1430 OS << " };\n"; in runTargetDesc()
1431 OS << "} // end anonymous namespace\n"; in runTargetDesc()
1435 OS << "\nstatic const TargetRegisterInfoDesc " in runTargetDesc()
1437 OS << " { 0, false },\n"; in runTargetDesc()
1441 OS << " { "; in runTargetDesc()
1442 OS << Reg.CostPerUse << ", " in runTargetDesc()
1446 OS << "};\n"; // End of register descriptors... in runTargetDesc()
1455 emitComposeSubRegIndices(OS, RegBank, ClassName); in runTargetDesc()
1456 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); in runTargetDesc()
1461 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1467 OS << " static const uint8_t Table["; in runTargetDesc()
1469 OS << " static const uint16_t Table["; in runTargetDesc()
1472 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1474 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1477 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1480 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1482 OS << " },\n"; in runTargetDesc()
1484 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1491 EmitRegUnitPressure(OS, RegBank, ClassName); in runTargetDesc()
1494 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1495 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1496 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; in runTargetDesc()
1497 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1498 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; in runTargetDesc()
1499 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1500 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1501 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1503 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1505 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1507 OS << ClassName << "::\n" << ClassName in runTargetDesc()
1514 printMask(OS, RegBank.CoveringLanes); in runTargetDesc()
1515 OS << ", RegClassInfos, HwMode) {\n" in runTargetDesc()
1530 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1532 OS << "}\n\n"; in runTargetDesc()
1543 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1546 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1547 OS << "0 };\n"; in runTargetDesc()
1562 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1564 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1565 OS << "};\n"; in runTargetDesc()
1567 OS << "\n\n"; in runTargetDesc()
1569 OS << "ArrayRef<const uint32_t *> " << ClassName in runTargetDesc()
1572 OS << " static const uint32_t *const Masks[] = {\n"; in runTargetDesc()
1574 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1575 OS << " };\n"; in runTargetDesc()
1576 OS << " return makeArrayRef(Masks);\n"; in runTargetDesc()
1578 OS << " return None;\n"; in runTargetDesc()
1580 OS << "}\n\n"; in runTargetDesc()
1582 OS << "ArrayRef<const char *> " << ClassName in runTargetDesc()
1585 OS << " static const char *const Names[] = {\n"; in runTargetDesc()
1587 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1588 OS << " };\n"; in runTargetDesc()
1589 OS << " return makeArrayRef(Names);\n"; in runTargetDesc()
1591 OS << " return None;\n"; in runTargetDesc()
1593 OS << "}\n\n"; in runTargetDesc()
1595 OS << "const " << TargetName << "FrameLowering *\n" << TargetName in runTargetDesc()
1601 OS << "} // end namespace llvm\n\n"; in runTargetDesc()
1602 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1605 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1607 runEnums(OS, Target, RegBank); in run()
1608 runMCDesc(OS, Target, RegBank); in run()
1609 runTargetHeader(OS, Target, RegBank); in run()
1610 runTargetDesc(OS, Target, RegBank); in run()
1616 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { in debugDump() argument
1627 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1628 OS << "\tSpillSize: {"; in debugDump()
1630 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
1631 OS << " }\n\tSpillAlignment: {"; in debugDump()
1633 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; in debugDump()
1634 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; in debugDump()
1635 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; in debugDump()
1636 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1637 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1638 OS << "\tRegs:"; in debugDump()
1640 OS << " " << R->getName(); in debugDump()
1642 OS << '\n'; in debugDump()
1643 OS << "\tSubClasses:"; in debugDump()
1648 OS << " " << SRC.getName(); in debugDump()
1650 OS << '\n'; in debugDump()
1651 OS << "\tSuperClasses:"; in debugDump()
1653 OS << " " << SRC->getName(); in debugDump()
1655 OS << '\n'; in debugDump()
1659 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1660 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1661 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
1665 OS << "Register " << R.getName() << ":\n"; in debugDump()
1666 OS << "\tCostPerUse: " << R.CostPerUse << '\n'; in debugDump()
1667 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; in debugDump()
1668 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; in debugDump()
1670 OS << "\tSubReg " << P.first->getName() in debugDump()
1678 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { in EmitRegisterInfo() argument
1679 RegisterInfoEmitter(RK).run(OS); in EmitRegisterInfo()