Lines Matching refs:CodeGenRegBank
63 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter()
68 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
71 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
75 CodeGenRegBank &Bank);
79 CodeGenRegBank &Bank);
92 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
94 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
96 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
104 CodeGenTarget &Target, CodeGenRegBank &Bank) { in runEnums()
195 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure()
694 CodeGenRegBank &RegBank, in emitComposeSubRegIndices()
764 CodeGenRegBank &RegBank, in emitComposeSubRegIndexLaneMask()
865 CodeGenRegBank &RegBank) { in runMCDesc()
1132 CodeGenRegBank &RegBank) { in runTargetHeader()
1202 CodeGenRegBank &RegBank){ in runTargetDesc()
1606 CodeGenRegBank &RegBank = Target.getRegBank(); in run()
1617 CodeGenRegBank &RegBank = Target.getRegBank(); in debugDump()