Lines Matching refs:opcode
904 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode, in EmulatePUSH() argument
934 if (ConditionPassed(opcode)) { in EmulatePUSH()
943 registers = Bits32(opcode, 7, 0); in EmulatePUSH()
945 if (Bit32(opcode, 8)) in EmulatePUSH()
953 registers = Bits32(opcode, 15, 0) & ~0xa000; in EmulatePUSH()
959 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
966 registers = Bits32(opcode, 15, 0); in EmulatePUSH()
972 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
1026 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode, in EmulatePOP() argument
1049 if (ConditionPassed(opcode)) { in EmulatePOP()
1058 registers = Bits32(opcode, 7, 0); in EmulatePOP()
1060 if (Bit32(opcode, 8)) in EmulatePOP()
1068 registers = Bits32(opcode, 15, 0) & ~0x2000; in EmulatePOP()
1071 if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14))) in EmulatePOP()
1079 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
1089 registers = Bits32(opcode, 15, 0); in EmulatePOP()
1095 if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) in EmulatePOP()
1099 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
1154 bool EmulateInstructionARM::EmulateADDRdSPImm(const uint32_t opcode, in EmulateADDRdSPImm() argument
1176 if (ConditionPassed(opcode)) { in EmulateADDRdSPImm()
1185 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) in EmulateADDRdSPImm()
1188 Rd = Bits32(opcode, 15, 12); in EmulateADDRdSPImm()
1189 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADDRdSPImm()
1215 bool EmulateInstructionARM::EmulateMOVRdSP(const uint32_t opcode, in EmulateMOVRdSP() argument
1237 if (ConditionPassed(opcode)) { in EmulateMOVRdSP()
1270 bool EmulateInstructionARM::EmulateMOVLowHigh(const uint32_t opcode, in EmulateMOVLowHigh() argument
1272 return EmulateMOVRdRm(opcode, encoding); in EmulateMOVLowHigh()
1277 bool EmulateInstructionARM::EmulateMOVRdRm(const uint32_t opcode, in EmulateMOVRdRm() argument
1299 if (ConditionPassed(opcode)) { in EmulateMOVRdRm()
1305 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateMOVRdRm()
1306 Rm = Bits32(opcode, 6, 3); in EmulateMOVRdRm()
1312 Rd = Bits32(opcode, 2, 0); in EmulateMOVRdRm()
1313 Rm = Bits32(opcode, 5, 3); in EmulateMOVRdRm()
1319 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdRm()
1320 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1321 setflags = BitIsSet(opcode, 20); in EmulateMOVRdRm()
1331 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdRm()
1332 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1333 setflags = BitIsSet(opcode, 20); in EmulateMOVRdRm()
1338 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMOVRdRm()
1366 bool EmulateInstructionARM::EmulateMOVRdImm(const uint32_t opcode, in EmulateMOVRdImm() argument
1386 if (ConditionPassed(opcode)) { in EmulateMOVRdImm()
1396 Rd = Bits32(opcode, 10, 8); in EmulateMOVRdImm()
1398 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) in EmulateMOVRdImm()
1404 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdImm()
1405 setflags = BitIsSet(opcode, 20); in EmulateMOVRdImm()
1406 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); in EmulateMOVRdImm()
1415 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdImm()
1417 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm()
1418 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateMOVRdImm()
1419 uint32_t i = Bit32(opcode, 26); in EmulateMOVRdImm()
1420 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateMOVRdImm()
1431 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdImm()
1432 setflags = BitIsSet(opcode, 20); in EmulateMOVRdImm()
1433 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); in EmulateMOVRdImm()
1438 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMOVRdImm()
1444 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdImm()
1446 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm()
1447 uint32_t imm12 = Bits32(opcode, 11, 0); in EmulateMOVRdImm()
1479 bool EmulateInstructionARM::EmulateMUL(const uint32_t opcode, in EmulateMUL() argument
1497 if (ConditionPassed(opcode)) { in EmulateMUL()
1507 d = Bits32(opcode, 2, 0); in EmulateMUL()
1508 n = Bits32(opcode, 5, 3); in EmulateMUL()
1509 m = Bits32(opcode, 2, 0); in EmulateMUL()
1520 d = Bits32(opcode, 11, 8); in EmulateMUL()
1521 n = Bits32(opcode, 19, 16); in EmulateMUL()
1522 m = Bits32(opcode, 3, 0); in EmulateMUL()
1533 d = Bits32(opcode, 19, 16); in EmulateMUL()
1534 n = Bits32(opcode, 3, 0); in EmulateMUL()
1535 m = Bits32(opcode, 11, 8); in EmulateMUL()
1536 setflags = BitIsSet(opcode, 20); in EmulateMUL()
1608 bool EmulateInstructionARM::EmulateMVNImm(const uint32_t opcode, in EmulateMVNImm() argument
1628 if (ConditionPassed(opcode)) { in EmulateMVNImm()
1635 Rd = Bits32(opcode, 11, 8); in EmulateMVNImm()
1636 setflags = BitIsSet(opcode, 20); in EmulateMVNImm()
1637 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); in EmulateMVNImm()
1640 Rd = Bits32(opcode, 15, 12); in EmulateMVNImm()
1641 setflags = BitIsSet(opcode, 20); in EmulateMVNImm()
1642 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); in EmulateMVNImm()
1647 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMVNImm()
1668 bool EmulateInstructionARM::EmulateMVNReg(const uint32_t opcode, in EmulateMVNReg() argument
1689 if (ConditionPassed(opcode)) { in EmulateMVNReg()
1698 Rd = Bits32(opcode, 2, 0); in EmulateMVNReg()
1699 Rm = Bits32(opcode, 5, 3); in EmulateMVNReg()
1707 Rd = Bits32(opcode, 11, 8); in EmulateMVNReg()
1708 Rm = Bits32(opcode, 3, 0); in EmulateMVNReg()
1709 setflags = BitIsSet(opcode, 20); in EmulateMVNReg()
1710 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateMVNReg()
1716 Rd = Bits32(opcode, 15, 12); in EmulateMVNReg()
1717 Rm = Bits32(opcode, 3, 0); in EmulateMVNReg()
1718 setflags = BitIsSet(opcode, 20); in EmulateMVNReg()
1719 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateMVNReg()
1749 bool EmulateInstructionARM::EmulateLDRRtPCRelative(const uint32_t opcode, in EmulateLDRRtPCRelative() argument
1771 if (ConditionPassed(opcode)) { in EmulateLDRRtPCRelative()
1792 Rt = Bits32(opcode, 10, 8); in EmulateLDRRtPCRelative()
1793 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32); in EmulateLDRRtPCRelative()
1797 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtPCRelative()
1798 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32); in EmulateLDRRtPCRelative()
1799 add = BitIsSet(opcode, 23); in EmulateLDRRtPCRelative()
1837 bool EmulateInstructionARM::EmulateADDSPImm(const uint32_t opcode, in EmulateADDSPImm() argument
1859 if (ConditionPassed(opcode)) { in EmulateADDSPImm()
1869 d = Bits32(opcode, 10, 8); in EmulateADDSPImm()
1870 imm32 = (Bits32(opcode, 7, 0) << 2); in EmulateADDSPImm()
1877 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) in EmulateADDSPImm()
1884 d = Bits32(opcode, 11, 8); in EmulateADDSPImm()
1885 imm32 = ThumbExpandImm(opcode); in EmulateADDSPImm()
1886 setflags = Bit32(opcode, 20); in EmulateADDSPImm()
1900 d = Bits32(opcode, 11, 8); in EmulateADDSPImm()
1902 uint32_t i = Bit32(opcode, 26); in EmulateADDSPImm()
1903 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDSPImm()
1904 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateADDSPImm()
1948 bool EmulateInstructionARM::EmulateADDSPRm(const uint32_t opcode, in EmulateADDSPRm() argument
1971 if (ConditionPassed(opcode)) { in EmulateADDSPRm()
1978 Rm = Bits32(opcode, 6, 3); in EmulateADDSPRm()
2009 bool EmulateInstructionARM::EmulateBLXImmediate(const uint32_t opcode, in EmulateBLXImmediate() argument
2031 if (ConditionPassed(opcode)) { in EmulateBLXImmediate()
2043 uint32_t S = Bit32(opcode, 26); in EmulateBLXImmediate()
2044 uint32_t imm10 = Bits32(opcode, 25, 16); in EmulateBLXImmediate()
2045 uint32_t J1 = Bit32(opcode, 13); in EmulateBLXImmediate()
2046 uint32_t J2 = Bit32(opcode, 11); in EmulateBLXImmediate()
2047 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateBLXImmediate()
2062 uint32_t S = Bit32(opcode, 26); in EmulateBLXImmediate()
2063 uint32_t imm10H = Bits32(opcode, 25, 16); in EmulateBLXImmediate()
2064 uint32_t J1 = Bit32(opcode, 13); in EmulateBLXImmediate()
2065 uint32_t J2 = Bit32(opcode, 11); in EmulateBLXImmediate()
2066 uint32_t imm10L = Bits32(opcode, 10, 1); in EmulateBLXImmediate()
2081 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); in EmulateBLXImmediate()
2088 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | in EmulateBLXImmediate()
2089 Bits32(opcode, 24, 24) << 1); in EmulateBLXImmediate()
2113 bool EmulateInstructionARM::EmulateBLXRm(const uint32_t opcode, in EmulateBLXRm() argument
2133 if (ConditionPassed(opcode)) { in EmulateBLXRm()
2144 Rm = Bits32(opcode, 6, 3); in EmulateBLXRm()
2153 Rm = Bits32(opcode, 3, 0); in EmulateBLXRm()
2178 bool EmulateInstructionARM::EmulateBXRm(const uint32_t opcode, in EmulateBXRm() argument
2189 if (ConditionPassed(opcode)) { in EmulateBXRm()
2195 Rm = Bits32(opcode, 6, 3); in EmulateBXRm()
2200 Rm = Bits32(opcode, 3, 0); in EmulateBXRm()
2226 bool EmulateInstructionARM::EmulateBXJRm(const uint32_t opcode, in EmulateBXJRm() argument
2243 if (ConditionPassed(opcode)) { in EmulateBXJRm()
2249 Rm = Bits32(opcode, 19, 16); in EmulateBXJRm()
2256 Rm = Bits32(opcode, 3, 0); in EmulateBXJRm()
2279 bool EmulateInstructionARM::EmulateSUBR7IPImm(const uint32_t opcode, in EmulateSUBR7IPImm() argument
2299 if (ConditionPassed(opcode)) { in EmulateSUBR7IPImm()
2307 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBR7IPImm()
2329 bool EmulateInstructionARM::EmulateSUBIPSPImm(const uint32_t opcode, in EmulateSUBIPSPImm() argument
2349 if (ConditionPassed(opcode)) { in EmulateSUBIPSPImm()
2357 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBIPSPImm()
2382 bool EmulateInstructionARM::EmulateSUBSPImm(const uint32_t opcode, in EmulateSUBSPImm() argument
2403 if (ConditionPassed(opcode)) { in EmulateSUBSPImm()
2415 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) in EmulateSUBSPImm()
2418 Rd = Bits32(opcode, 11, 8); in EmulateSUBSPImm()
2419 setflags = BitIsSet(opcode, 20); in EmulateSUBSPImm()
2420 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSUBSPImm()
2422 return EmulateCMPImm(opcode, eEncodingT2); in EmulateSUBSPImm()
2427 Rd = Bits32(opcode, 11, 8); in EmulateSUBSPImm()
2429 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateSUBSPImm()
2434 Rd = Bits32(opcode, 15, 12); in EmulateSUBSPImm()
2435 setflags = BitIsSet(opcode, 20); in EmulateSUBSPImm()
2436 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBSPImm()
2441 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBSPImm()
2468 bool EmulateInstructionARM::EmulateSTRRtSP(const uint32_t opcode, in EmulateSTRRtSP() argument
2483 if (ConditionPassed(opcode)) { in EmulateSTRRtSP()
2498 Rt = Bits32(opcode, 15, 12); in EmulateSTRRtSP()
2499 imm12 = Bits32(opcode, 11, 0); in EmulateSTRRtSP()
2500 Rn = Bits32(opcode, 19, 16); in EmulateSTRRtSP()
2505 index = BitIsSet(opcode, 24); in EmulateSTRRtSP()
2506 add = BitIsSet(opcode, 23); in EmulateSTRRtSP()
2507 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRRtSP()
2562 bool EmulateInstructionARM::EmulateVPUSH(const uint32_t opcode, in EmulateVPUSH() argument
2585 if (ConditionPassed(opcode)) { in EmulateVPUSH()
2598 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); in EmulateVPUSH()
2599 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPUSH()
2601 regs = Bits32(opcode, 7, 0) / 2; in EmulateVPUSH()
2609 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); in EmulateVPUSH()
2610 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPUSH()
2611 regs = Bits32(opcode, 7, 0); in EmulateVPUSH()
2655 bool EmulateInstructionARM::EmulateVPOP(const uint32_t opcode, in EmulateVPOP() argument
2677 if (ConditionPassed(opcode)) { in EmulateVPOP()
2690 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); in EmulateVPOP()
2691 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPOP()
2693 regs = Bits32(opcode, 7, 0) / 2; in EmulateVPOP()
2701 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); in EmulateVPOP()
2702 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPOP()
2703 regs = Bits32(opcode, 7, 0); in EmulateVPOP()
2746 bool EmulateInstructionARM::EmulateSVC(const uint32_t opcode, in EmulateSVC() argument
2759 if (ConditionPassed(opcode)) { in EmulateSVC()
2769 imm32 = Bits32(opcode, 7, 0); in EmulateSVC()
2774 imm32 = Bits32(opcode, 23, 0); in EmulateSVC()
2792 bool EmulateInstructionARM::EmulateIT(const uint32_t opcode, in EmulateIT() argument
2800 m_it_session.InitIT(Bits32(opcode, 7, 0)); in EmulateIT()
2804 bool EmulateInstructionARM::EmulateNop(const uint32_t opcode, in EmulateNop() argument
2811 bool EmulateInstructionARM::EmulateB(const uint32_t opcode, in EmulateB() argument
2824 if (ConditionPassed(opcode)) { in EmulateB()
2835 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1); in EmulateB()
2840 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1); in EmulateB()
2847 if (Bits32(opcode, 25, 23) == 7) in EmulateB()
2851 uint32_t S = Bit32(opcode, 26); in EmulateB()
2852 uint32_t imm6 = Bits32(opcode, 21, 16); in EmulateB()
2853 uint32_t J1 = Bit32(opcode, 13); in EmulateB()
2854 uint32_t J2 = Bit32(opcode, 11); in EmulateB()
2855 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateB()
2864 uint32_t S = Bit32(opcode, 26); in EmulateB()
2865 uint32_t imm10 = Bits32(opcode, 25, 16); in EmulateB()
2866 uint32_t J1 = Bit32(opcode, 13); in EmulateB()
2867 uint32_t J2 = Bit32(opcode, 11); in EmulateB()
2868 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateB()
2879 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); in EmulateB()
2895 bool EmulateInstructionARM::EmulateCB(const uint32_t opcode, in EmulateCB() argument
2907 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success); in EmulateCB()
2922 imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1; in EmulateCB()
2923 nonzero = BitIsSet(opcode, 11); in EmulateCB()
2949 bool EmulateInstructionARM::EmulateTB(const uint32_t opcode, in EmulateTB() argument
2963 if (ConditionPassed(opcode)) { in EmulateTB()
2971 Rn = Bits32(opcode, 19, 16); in EmulateTB()
2972 Rm = Bits32(opcode, 3, 0); in EmulateTB()
2973 is_tbh = BitIsSet(opcode, 4); in EmulateTB()
3023 bool EmulateInstructionARM::EmulateADDImmThumb(const uint32_t opcode, in EmulateADDImmThumb() argument
3039 if (ConditionPassed(opcode)) { in EmulateADDImmThumb()
3051 d = Bits32(opcode, 2, 0); in EmulateADDImmThumb()
3052 n = Bits32(opcode, 5, 3); in EmulateADDImmThumb()
3054 imm32 = Bits32(opcode, 8, 6); in EmulateADDImmThumb()
3061 d = Bits32(opcode, 10, 8); in EmulateADDImmThumb()
3062 n = Bits32(opcode, 10, 8); in EmulateADDImmThumb()
3064 imm32 = Bits32(opcode, 7, 0); in EmulateADDImmThumb()
3072 d = Bits32(opcode, 11, 8); in EmulateADDImmThumb()
3073 n = Bits32(opcode, 19, 16); in EmulateADDImmThumb()
3074 setflags = BitIsSet(opcode, 20); in EmulateADDImmThumb()
3075 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry_out); in EmulateADDImmThumb()
3079 return EmulateADDSPImm(opcode, eEncodingT3); in EmulateADDImmThumb()
3091 d = Bits32(opcode, 11, 8); in EmulateADDImmThumb()
3092 n = Bits32(opcode, 19, 16); in EmulateADDImmThumb()
3094 uint32_t i = Bit32(opcode, 26); in EmulateADDImmThumb()
3095 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDImmThumb()
3096 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateADDImmThumb()
3101 return EmulateADDSPImm(opcode, eEncodingT4); in EmulateADDImmThumb()
3145 bool EmulateInstructionARM::EmulateADDImmARM(const uint32_t opcode, in EmulateADDImmARM() argument
3165 if (ConditionPassed(opcode)) { in EmulateADDImmARM()
3172 Rd = Bits32(opcode, 15, 12); in EmulateADDImmARM()
3173 Rn = Bits32(opcode, 19, 16); in EmulateADDImmARM()
3174 setflags = BitIsSet(opcode, 20); in EmulateADDImmARM()
3175 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADDImmARM()
3210 bool EmulateInstructionARM::EmulateADDReg(const uint32_t opcode, in EmulateADDReg() argument
3231 if (ConditionPassed(opcode)) { in EmulateADDReg()
3238 Rd = Bits32(opcode, 2, 0); in EmulateADDReg()
3239 Rn = Bits32(opcode, 5, 3); in EmulateADDReg()
3240 Rm = Bits32(opcode, 8, 6); in EmulateADDReg()
3246 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateADDReg()
3247 Rm = Bits32(opcode, 6, 3); in EmulateADDReg()
3257 Rd = Bits32(opcode, 15, 12); in EmulateADDReg()
3258 Rn = Bits32(opcode, 19, 16); in EmulateADDReg()
3259 Rm = Bits32(opcode, 3, 0); in EmulateADDReg()
3260 setflags = BitIsSet(opcode, 20); in EmulateADDReg()
3261 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateADDReg()
3299 bool EmulateInstructionARM::EmulateCMNImm(const uint32_t opcode, in EmulateCMNImm() argument
3318 Rn = Bits32(opcode, 19, 16); in EmulateCMNImm()
3319 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateCMNImm()
3324 Rn = Bits32(opcode, 19, 16); in EmulateCMNImm()
3325 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateCMNImm()
3346 bool EmulateInstructionARM::EmulateCMNReg(const uint32_t opcode, in EmulateCMNReg() argument
3368 Rn = Bits32(opcode, 2, 0); in EmulateCMNReg()
3369 Rm = Bits32(opcode, 5, 3); in EmulateCMNReg()
3374 Rn = Bits32(opcode, 19, 16); in EmulateCMNReg()
3375 Rm = Bits32(opcode, 3, 0); in EmulateCMNReg()
3376 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateCMNReg()
3382 Rn = Bits32(opcode, 19, 16); in EmulateCMNReg()
3383 Rm = Bits32(opcode, 3, 0); in EmulateCMNReg()
3384 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateCMNReg()
3412 bool EmulateInstructionARM::EmulateCMPImm(const uint32_t opcode, in EmulateCMPImm() argument
3431 Rn = Bits32(opcode, 10, 8); in EmulateCMPImm()
3432 imm32 = Bits32(opcode, 7, 0); in EmulateCMPImm()
3435 Rn = Bits32(opcode, 19, 16); in EmulateCMPImm()
3436 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateCMPImm()
3441 Rn = Bits32(opcode, 19, 16); in EmulateCMPImm()
3442 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateCMPImm()
3463 bool EmulateInstructionARM::EmulateCMPReg(const uint32_t opcode, in EmulateCMPReg() argument
3485 Rn = Bits32(opcode, 2, 0); in EmulateCMPReg()
3486 Rm = Bits32(opcode, 5, 3); in EmulateCMPReg()
3491 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateCMPReg()
3492 Rm = Bits32(opcode, 6, 3); in EmulateCMPReg()
3501 Rn = Bits32(opcode, 19, 16); in EmulateCMPReg()
3502 Rm = Bits32(opcode, 3, 0); in EmulateCMPReg()
3503 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateCMPReg()
3508 Rn = Bits32(opcode, 19, 16); in EmulateCMPReg()
3509 Rm = Bits32(opcode, 3, 0); in EmulateCMPReg()
3510 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateCMPReg()
3540 bool EmulateInstructionARM::EmulateASRImm(const uint32_t opcode, in EmulateASRImm() argument
3558 return EmulateShiftImm(opcode, encoding, SRType_ASR); in EmulateASRImm()
3566 bool EmulateInstructionARM::EmulateASRReg(const uint32_t opcode, in EmulateASRReg() argument
3582 return EmulateShiftReg(opcode, encoding, SRType_ASR); in EmulateASRReg()
3588 bool EmulateInstructionARM::EmulateLSLImm(const uint32_t opcode, in EmulateLSLImm() argument
3606 return EmulateShiftImm(opcode, encoding, SRType_LSL); in EmulateLSLImm()
3613 bool EmulateInstructionARM::EmulateLSLReg(const uint32_t opcode, in EmulateLSLReg() argument
3629 return EmulateShiftReg(opcode, encoding, SRType_LSL); in EmulateLSLReg()
3636 bool EmulateInstructionARM::EmulateLSRImm(const uint32_t opcode, in EmulateLSRImm() argument
3654 return EmulateShiftImm(opcode, encoding, SRType_LSR); in EmulateLSRImm()
3661 bool EmulateInstructionARM::EmulateLSRReg(const uint32_t opcode, in EmulateLSRReg() argument
3677 return EmulateShiftReg(opcode, encoding, SRType_LSR); in EmulateLSRReg()
3684 bool EmulateInstructionARM::EmulateRORImm(const uint32_t opcode, in EmulateRORImm() argument
3702 return EmulateShiftImm(opcode, encoding, SRType_ROR); in EmulateRORImm()
3710 bool EmulateInstructionARM::EmulateRORReg(const uint32_t opcode, in EmulateRORReg() argument
3726 return EmulateShiftReg(opcode, encoding, SRType_ROR); in EmulateRORReg()
3734 bool EmulateInstructionARM::EmulateRRX(const uint32_t opcode, in EmulateRRX() argument
3752 return EmulateShiftImm(opcode, encoding, SRType_RRX); in EmulateRRX()
3755 bool EmulateInstructionARM::EmulateShiftImm(const uint32_t opcode, in EmulateShiftImm() argument
3766 if (ConditionPassed(opcode)) { in EmulateShiftImm()
3789 Rd = Bits32(opcode, 2, 0); in EmulateShiftImm()
3790 Rm = Bits32(opcode, 5, 3); in EmulateShiftImm()
3792 imm5 = Bits32(opcode, 10, 6); in EmulateShiftImm()
3800 Rd = Bits32(opcode, 11, 8); in EmulateShiftImm()
3801 Rm = Bits32(opcode, 3, 0); in EmulateShiftImm()
3802 setflags = BitIsSet(opcode, 20); in EmulateShiftImm()
3803 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); in EmulateShiftImm()
3808 Rd = Bits32(opcode, 15, 12); in EmulateShiftImm()
3809 Rm = Bits32(opcode, 3, 0); in EmulateShiftImm()
3810 setflags = BitIsSet(opcode, 20); in EmulateShiftImm()
3811 imm5 = Bits32(opcode, 11, 7); in EmulateShiftImm()
3845 bool EmulateInstructionARM::EmulateShiftReg(const uint32_t opcode, in EmulateShiftReg() argument
3855 if (ConditionPassed(opcode)) { in EmulateShiftReg()
3864 Rd = Bits32(opcode, 2, 0); in EmulateShiftReg()
3866 Rm = Bits32(opcode, 5, 3); in EmulateShiftReg()
3870 Rd = Bits32(opcode, 11, 8); in EmulateShiftReg()
3871 Rn = Bits32(opcode, 19, 16); in EmulateShiftReg()
3872 Rm = Bits32(opcode, 3, 0); in EmulateShiftReg()
3873 setflags = BitIsSet(opcode, 20); in EmulateShiftReg()
3878 Rd = Bits32(opcode, 15, 12); in EmulateShiftReg()
3879 Rn = Bits32(opcode, 3, 0); in EmulateShiftReg()
3880 Rm = Bits32(opcode, 11, 8); in EmulateShiftReg()
3881 setflags = BitIsSet(opcode, 20); in EmulateShiftReg()
3919 bool EmulateInstructionARM::EmulateLDM(const uint32_t opcode, in EmulateLDM() argument
3939 if (ConditionPassed(opcode)) { in EmulateLDM()
3948 n = Bits32(opcode, 10, 8); in EmulateLDM()
3949 registers = Bits32(opcode, 7, 0); in EmulateLDM()
3959 n = Bits32(opcode, 19, 16); in EmulateLDM()
3960 registers = Bits32(opcode, 15, 0); in EmulateLDM()
3962 wback = BitIsSet(opcode, 21); in EmulateLDM()
3967 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15))) in EmulateLDM()
3981 n = Bits32(opcode, 19, 16); in EmulateLDM()
3982 registers = Bits32(opcode, 15, 0); in EmulateLDM()
3983 wback = BitIsSet(opcode, 21); in EmulateLDM()
4062 bool EmulateInstructionARM::EmulateLDMDA(const uint32_t opcode, in EmulateLDMDA() argument
4083 if (ConditionPassed(opcode)) { in EmulateLDMDA()
4093 n = Bits32(opcode, 19, 16); in EmulateLDMDA()
4094 registers = Bits32(opcode, 15, 0); in EmulateLDMDA()
4095 wback = BitIsSet(opcode, 21); in EmulateLDMDA()
4179 bool EmulateInstructionARM::EmulateLDMDB(const uint32_t opcode, in EmulateLDMDB() argument
4199 if (ConditionPassed(opcode)) { in EmulateLDMDB()
4207 n = Bits32(opcode, 19, 16); in EmulateLDMDB()
4208 registers = Bits32(opcode, 15, 0); in EmulateLDMDB()
4210 wback = BitIsSet(opcode, 21); in EmulateLDMDB()
4215 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15))) in EmulateLDMDB()
4231 n = Bits32(opcode, 19, 16); in EmulateLDMDB()
4232 registers = Bits32(opcode, 15, 0); in EmulateLDMDB()
4233 wback = BitIsSet(opcode, 21); in EmulateLDMDB()
4318 bool EmulateInstructionARM::EmulateLDMIB(const uint32_t opcode, in EmulateLDMIB() argument
4337 if (ConditionPassed(opcode)) { in EmulateLDMIB()
4345 n = Bits32(opcode, 19, 16); in EmulateLDMIB()
4346 registers = Bits32(opcode, 15, 0); in EmulateLDMIB()
4347 wback = BitIsSet(opcode, 21); in EmulateLDMIB()
4430 bool EmulateInstructionARM::EmulateLDRRtRnImm(const uint32_t opcode, in EmulateLDRRtRnImm() argument
4451 if (ConditionPassed(opcode)) { in EmulateLDRRtRnImm()
4461 Rt = Bits32(opcode, 2, 0); in EmulateLDRRtRnImm()
4462 Rn = Bits32(opcode, 5, 3); in EmulateLDRRtRnImm()
4463 imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32); in EmulateLDRRtRnImm()
4473 Rt = Bits32(opcode, 10, 8); in EmulateLDRRtRnImm()
4475 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateLDRRtRnImm()
4487 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtRnImm()
4488 Rn = Bits32(opcode, 19, 16); in EmulateLDRRtRnImm()
4489 imm32 = Bits32(opcode, 11, 0); in EmulateLDRRtRnImm()
4508 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRRtRnImm()
4512 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtRnImm()
4513 Rn = Bits32(opcode, 19, 16); in EmulateLDRRtRnImm()
4514 imm32 = Bits32(opcode, 7, 0); in EmulateLDRRtRnImm()
4517 index = BitIsSet(opcode, 10); in EmulateLDRRtRnImm()
4518 add = BitIsSet(opcode, 9); in EmulateLDRRtRnImm()
4519 wback = BitIsSet(opcode, 8); in EmulateLDRRtRnImm()
4593 bool EmulateInstructionARM::EmulateSTM(const uint32_t opcode, in EmulateSTM() argument
4615 if (ConditionPassed(opcode)) { in EmulateSTM()
4625 n = Bits32(opcode, 10, 8); in EmulateSTM()
4626 registers = Bits32(opcode, 7, 0); in EmulateSTM()
4638 n = Bits32(opcode, 19, 16); in EmulateSTM()
4639 registers = Bits32(opcode, 15, 0); in EmulateSTM()
4641 wback = BitIsSet(opcode, 21); in EmulateSTM()
4655 n = Bits32(opcode, 19, 16); in EmulateSTM()
4656 registers = Bits32(opcode, 15, 0); in EmulateSTM()
4657 wback = BitIsSet(opcode, 21); in EmulateSTM()
4745 bool EmulateInstructionARM::EmulateSTMDA(const uint32_t opcode, in EmulateSTMDA() argument
4768 if (ConditionPassed(opcode)) { in EmulateSTMDA()
4778 n = Bits32(opcode, 19, 16); in EmulateSTMDA()
4779 registers = Bits32(opcode, 15, 0); in EmulateSTMDA()
4780 wback = BitIsSet(opcode, 21); in EmulateSTMDA()
4867 bool EmulateInstructionARM::EmulateSTMDB(const uint32_t opcode, in EmulateSTMDB() argument
4890 if (ConditionPassed(opcode)) { in EmulateSTMDB()
4900 if ((BitIsSet(opcode, 21)) && (Bits32(opcode, 19, 16) == 13)) { in EmulateSTMDB()
4904 n = Bits32(opcode, 19, 16); in EmulateSTMDB()
4905 registers = Bits32(opcode, 15, 0); in EmulateSTMDB()
4907 wback = BitIsSet(opcode, 21); in EmulateSTMDB()
4919 if (BitIsSet(opcode, 21) && (Bits32(opcode, 19, 16) == 13) && in EmulateSTMDB()
4920 BitCount(Bits32(opcode, 15, 0)) >= 2) { in EmulateSTMDB()
4924 n = Bits32(opcode, 19, 16); in EmulateSTMDB()
4925 registers = Bits32(opcode, 15, 0); in EmulateSTMDB()
4926 wback = BitIsSet(opcode, 21); in EmulateSTMDB()
5016 bool EmulateInstructionARM::EmulateSTMIB(const uint32_t opcode, in EmulateSTMIB() argument
5039 if (ConditionPassed(opcode)) { in EmulateSTMIB()
5049 n = Bits32(opcode, 19, 16); in EmulateSTMIB()
5050 registers = Bits32(opcode, 15, 0); in EmulateSTMIB()
5051 wback = BitIsSet(opcode, 21); in EmulateSTMIB()
5138 bool EmulateInstructionARM::EmulateSTRThumb(const uint32_t opcode, in EmulateSTRThumb() argument
5154 if (ConditionPassed(opcode)) { in EmulateSTRThumb()
5167 t = Bits32(opcode, 2, 0); in EmulateSTRThumb()
5168 n = Bits32(opcode, 5, 3); in EmulateSTRThumb()
5169 imm32 = Bits32(opcode, 10, 6) << 2; in EmulateSTRThumb()
5179 t = Bits32(opcode, 10, 8); in EmulateSTRThumb()
5181 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTRThumb()
5191 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRThumb()
5195 t = Bits32(opcode, 15, 12); in EmulateSTRThumb()
5196 n = Bits32(opcode, 19, 16); in EmulateSTRThumb()
5197 imm32 = Bits32(opcode, 11, 0); in EmulateSTRThumb()
5214 if ((Bits32(opcode, 19, 16) == 15) || in EmulateSTRThumb()
5215 (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))) in EmulateSTRThumb()
5219 t = Bits32(opcode, 15, 12); in EmulateSTRThumb()
5220 n = Bits32(opcode, 19, 16); in EmulateSTRThumb()
5221 imm32 = Bits32(opcode, 7, 0); in EmulateSTRThumb()
5224 index = BitIsSet(opcode, 10); in EmulateSTRThumb()
5225 add = BitIsSet(opcode, 9); in EmulateSTRThumb()
5226 wback = BitIsSet(opcode, 8); in EmulateSTRThumb()
5305 bool EmulateInstructionARM::EmulateSTRRegister(const uint32_t opcode, in EmulateSTRRegister() argument
5326 if (ConditionPassed(opcode)) { in EmulateSTRRegister()
5344 t = Bits32(opcode, 2, 0); in EmulateSTRRegister()
5345 n = Bits32(opcode, 5, 3); in EmulateSTRRegister()
5346 m = Bits32(opcode, 8, 6); in EmulateSTRRegister()
5360 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRRegister()
5364 t = Bits32(opcode, 15, 12); in EmulateSTRRegister()
5365 n = Bits32(opcode, 19, 16); in EmulateSTRRegister()
5366 m = Bits32(opcode, 3, 0); in EmulateSTRRegister()
5375 shift_n = Bits32(opcode, 5, 4); in EmulateSTRRegister()
5385 t = Bits32(opcode, 15, 12); in EmulateSTRRegister()
5386 n = Bits32(opcode, 19, 16); in EmulateSTRRegister()
5387 m = Bits32(opcode, 3, 0); in EmulateSTRRegister()
5391 index = BitIsSet(opcode, 24); in EmulateSTRRegister()
5392 add = BitIsSet(opcode, 23); in EmulateSTRRegister()
5393 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRRegister()
5396 uint32_t typ = Bits32(opcode, 6, 5); in EmulateSTRRegister()
5397 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateSTRRegister()
5495 bool EmulateInstructionARM::EmulateSTRBThumb(const uint32_t opcode, in EmulateSTRBThumb() argument
5508 if (ConditionPassed(opcode)) { in EmulateSTRBThumb()
5519 t = Bits32(opcode, 2, 0); in EmulateSTRBThumb()
5520 n = Bits32(opcode, 5, 3); in EmulateSTRBThumb()
5521 imm32 = Bits32(opcode, 10, 6); in EmulateSTRBThumb()
5531 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRBThumb()
5535 t = Bits32(opcode, 15, 12); in EmulateSTRBThumb()
5536 n = Bits32(opcode, 19, 16); in EmulateSTRBThumb()
5537 imm32 = Bits32(opcode, 11, 0); in EmulateSTRBThumb()
5552 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRBThumb()
5556 t = Bits32(opcode, 15, 12); in EmulateSTRBThumb()
5557 n = Bits32(opcode, 19, 16); in EmulateSTRBThumb()
5558 imm32 = Bits32(opcode, 7, 0); in EmulateSTRBThumb()
5561 index = BitIsSet(opcode, 10); in EmulateSTRBThumb()
5562 add = BitIsSet(opcode, 9); in EmulateSTRBThumb()
5563 wback = BitIsSet(opcode, 8); in EmulateSTRBThumb()
5632 bool EmulateInstructionARM::EmulateSTRHRegister(const uint32_t opcode, in EmulateSTRHRegister() argument
5649 if (ConditionPassed(opcode)) { in EmulateSTRHRegister()
5665 t = Bits32(opcode, 2, 0); in EmulateSTRHRegister()
5666 n = Bits32(opcode, 5, 3); in EmulateSTRHRegister()
5667 m = Bits32(opcode, 8, 6); in EmulateSTRHRegister()
5683 t = Bits32(opcode, 15, 12); in EmulateSTRHRegister()
5684 n = Bits32(opcode, 19, 16); in EmulateSTRHRegister()
5685 m = Bits32(opcode, 3, 0); in EmulateSTRHRegister()
5696 shift_n = Bits32(opcode, 5, 4); in EmulateSTRHRegister()
5707 t = Bits32(opcode, 15, 12); in EmulateSTRHRegister()
5708 n = Bits32(opcode, 19, 16); in EmulateSTRHRegister()
5709 m = Bits32(opcode, 3, 0); in EmulateSTRHRegister()
5713 index = BitIsSet(opcode, 24); in EmulateSTRHRegister()
5714 add = BitIsSet(opcode, 23); in EmulateSTRHRegister()
5715 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRHRegister()
5810 bool EmulateInstructionARM::EmulateADCImm(const uint32_t opcode, in EmulateADCImm() argument
5830 if (ConditionPassed(opcode)) { in EmulateADCImm()
5837 Rd = Bits32(opcode, 11, 8); in EmulateADCImm()
5838 Rn = Bits32(opcode, 19, 16); in EmulateADCImm()
5839 setflags = BitIsSet(opcode, 20); in EmulateADCImm()
5840 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateADCImm()
5845 Rd = Bits32(opcode, 15, 12); in EmulateADCImm()
5846 Rn = Bits32(opcode, 19, 16); in EmulateADCImm()
5847 setflags = BitIsSet(opcode, 20); in EmulateADCImm()
5848 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADCImm()
5851 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateADCImm()
5879 bool EmulateInstructionARM::EmulateADCReg(const uint32_t opcode, in EmulateADCReg() argument
5900 if (ConditionPassed(opcode)) { in EmulateADCReg()
5907 Rd = Rn = Bits32(opcode, 2, 0); in EmulateADCReg()
5908 Rm = Bits32(opcode, 5, 3); in EmulateADCReg()
5914 Rd = Bits32(opcode, 11, 8); in EmulateADCReg()
5915 Rn = Bits32(opcode, 19, 16); in EmulateADCReg()
5916 Rm = Bits32(opcode, 3, 0); in EmulateADCReg()
5917 setflags = BitIsSet(opcode, 20); in EmulateADCReg()
5918 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateADCReg()
5923 Rd = Bits32(opcode, 15, 12); in EmulateADCReg()
5924 Rn = Bits32(opcode, 19, 16); in EmulateADCReg()
5925 Rm = Bits32(opcode, 3, 0); in EmulateADCReg()
5926 setflags = BitIsSet(opcode, 20); in EmulateADCReg()
5927 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateADCReg()
5930 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateADCReg()
5964 bool EmulateInstructionARM::EmulateADR(const uint32_t opcode, in EmulateADR() argument
5979 if (ConditionPassed(opcode)) { in EmulateADR()
5985 Rd = Bits32(opcode, 10, 8); in EmulateADR()
5986 imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32) in EmulateADR()
5991 Rd = Bits32(opcode, 11, 8); in EmulateADR()
5992 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateADR()
5993 add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB in EmulateADR()
5999 Rd = Bits32(opcode, 15, 12); in EmulateADR()
6000 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADR()
6001 add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB in EmulateADR()
6027 bool EmulateInstructionARM::EmulateANDImm(const uint32_t opcode, in EmulateANDImm() argument
6047 if (ConditionPassed(opcode)) { in EmulateANDImm()
6055 Rd = Bits32(opcode, 11, 8); in EmulateANDImm()
6056 Rn = Bits32(opcode, 19, 16); in EmulateANDImm()
6057 setflags = BitIsSet(opcode, 20); in EmulateANDImm()
6059 opcode, APSR_C, in EmulateANDImm()
6063 return EmulateTSTImm(opcode, eEncodingT1); in EmulateANDImm()
6068 Rd = Bits32(opcode, 15, 12); in EmulateANDImm()
6069 Rn = Bits32(opcode, 19, 16); in EmulateANDImm()
6070 setflags = BitIsSet(opcode, 20); in EmulateANDImm()
6072 ARMExpandImm_C(opcode, APSR_C, in EmulateANDImm()
6076 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateANDImm()
6102 bool EmulateInstructionARM::EmulateANDReg(const uint32_t opcode, in EmulateANDReg() argument
6123 if (ConditionPassed(opcode)) { in EmulateANDReg()
6131 Rd = Rn = Bits32(opcode, 2, 0); in EmulateANDReg()
6132 Rm = Bits32(opcode, 5, 3); in EmulateANDReg()
6138 Rd = Bits32(opcode, 11, 8); in EmulateANDReg()
6139 Rn = Bits32(opcode, 19, 16); in EmulateANDReg()
6140 Rm = Bits32(opcode, 3, 0); in EmulateANDReg()
6141 setflags = BitIsSet(opcode, 20); in EmulateANDReg()
6142 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateANDReg()
6145 return EmulateTSTReg(opcode, eEncodingT2); in EmulateANDReg()
6150 Rd = Bits32(opcode, 15, 12); in EmulateANDReg()
6151 Rn = Bits32(opcode, 19, 16); in EmulateANDReg()
6152 Rm = Bits32(opcode, 3, 0); in EmulateANDReg()
6153 setflags = BitIsSet(opcode, 20); in EmulateANDReg()
6154 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateANDReg()
6157 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateANDReg()
6192 bool EmulateInstructionARM::EmulateBICImm(const uint32_t opcode, in EmulateBICImm() argument
6212 if (ConditionPassed(opcode)) { in EmulateBICImm()
6220 Rd = Bits32(opcode, 11, 8); in EmulateBICImm()
6221 Rn = Bits32(opcode, 19, 16); in EmulateBICImm()
6222 setflags = BitIsSet(opcode, 20); in EmulateBICImm()
6224 opcode, APSR_C, in EmulateBICImm()
6230 Rd = Bits32(opcode, 15, 12); in EmulateBICImm()
6231 Rn = Bits32(opcode, 19, 16); in EmulateBICImm()
6232 setflags = BitIsSet(opcode, 20); in EmulateBICImm()
6234 ARMExpandImm_C(opcode, APSR_C, in EmulateBICImm()
6240 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateBICImm()
6267 bool EmulateInstructionARM::EmulateBICReg(const uint32_t opcode, in EmulateBICReg() argument
6288 if (ConditionPassed(opcode)) { in EmulateBICReg()
6296 Rd = Rn = Bits32(opcode, 2, 0); in EmulateBICReg()
6297 Rm = Bits32(opcode, 5, 3); in EmulateBICReg()
6303 Rd = Bits32(opcode, 11, 8); in EmulateBICReg()
6304 Rn = Bits32(opcode, 19, 16); in EmulateBICReg()
6305 Rm = Bits32(opcode, 3, 0); in EmulateBICReg()
6306 setflags = BitIsSet(opcode, 20); in EmulateBICReg()
6307 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateBICReg()
6312 Rd = Bits32(opcode, 15, 12); in EmulateBICReg()
6313 Rn = Bits32(opcode, 19, 16); in EmulateBICReg()
6314 Rm = Bits32(opcode, 3, 0); in EmulateBICReg()
6315 setflags = BitIsSet(opcode, 20); in EmulateBICReg()
6316 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateBICReg()
6321 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateBICReg()
6356 bool EmulateInstructionARM::EmulateLDRImmediateARM(const uint32_t opcode, in EmulateLDRImmediateARM() argument
6375 if (ConditionPassed(opcode)) { in EmulateLDRImmediateARM()
6392 t = Bits32(opcode, 15, 12); in EmulateLDRImmediateARM()
6393 n = Bits32(opcode, 19, 16); in EmulateLDRImmediateARM()
6394 imm32 = Bits32(opcode, 11, 0); in EmulateLDRImmediateARM()
6398 index = BitIsSet(opcode, 24); in EmulateLDRImmediateARM()
6399 add = BitIsSet(opcode, 23); in EmulateLDRImmediateARM()
6400 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRImmediateARM()
6493 bool EmulateInstructionARM::EmulateLDRRegister(const uint32_t opcode, in EmulateLDRRegister() argument
6516 if (ConditionPassed(opcode)) { in EmulateLDRRegister()
6533 t = Bits32(opcode, 2, 0); in EmulateLDRRegister()
6534 n = Bits32(opcode, 5, 3); in EmulateLDRRegister()
6535 m = Bits32(opcode, 8, 6); in EmulateLDRRegister()
6551 t = Bits32(opcode, 15, 12); in EmulateLDRRegister()
6552 n = Bits32(opcode, 19, 16); in EmulateLDRRegister()
6553 m = Bits32(opcode, 3, 0); in EmulateLDRRegister()
6562 shift_n = Bits32(opcode, 5, 4); in EmulateLDRRegister()
6577 t = Bits32(opcode, 15, 12); in EmulateLDRRegister()
6578 n = Bits32(opcode, 19, 16); in EmulateLDRRegister()
6579 m = Bits32(opcode, 3, 0); in EmulateLDRRegister()
6583 index = BitIsSet(opcode, 24); in EmulateLDRRegister()
6584 add = BitIsSet(opcode, 23); in EmulateLDRRegister()
6585 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRRegister()
6588 uint32_t type = Bits32(opcode, 6, 5); in EmulateLDRRegister()
6589 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRRegister()
6700 bool EmulateInstructionARM::EmulateLDRBImmediate(const uint32_t opcode, in EmulateLDRBImmediate() argument
6713 if (ConditionPassed(opcode)) { in EmulateLDRBImmediate()
6725 t = Bits32(opcode, 2, 0); in EmulateLDRBImmediate()
6726 n = Bits32(opcode, 5, 3); in EmulateLDRBImmediate()
6727 imm32 = Bits32(opcode, 10, 6); in EmulateLDRBImmediate()
6738 t = Bits32(opcode, 15, 12); in EmulateLDRBImmediate()
6739 n = Bits32(opcode, 19, 16); in EmulateLDRBImmediate()
6740 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBImmediate()
6753 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBImmediate()
6764 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRBImmediate()
6768 t = Bits32(opcode, 15, 12); in EmulateLDRBImmediate()
6769 n = Bits32(opcode, 19, 16); in EmulateLDRBImmediate()
6770 imm32 = Bits32(opcode, 7, 0); in EmulateLDRBImmediate()
6773 index = BitIsSet(opcode, 10); in EmulateLDRBImmediate()
6774 add = BitIsSet(opcode, 9); in EmulateLDRBImmediate()
6775 wback = BitIsSet(opcode, 8); in EmulateLDRBImmediate()
6783 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBImmediate()
6847 bool EmulateInstructionARM::EmulateLDRBLiteral(const uint32_t opcode, in EmulateLDRBLiteral() argument
6859 if (ConditionPassed(opcode)) { in EmulateLDRBLiteral()
6866 t = Bits32(opcode, 15, 12); in EmulateLDRBLiteral()
6867 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBLiteral()
6868 add = BitIsSet(opcode, 23); in EmulateLDRBLiteral()
6882 t = Bits32(opcode, 15, 12); in EmulateLDRBLiteral()
6883 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBLiteral()
6884 add = BitIsSet(opcode, 23); in EmulateLDRBLiteral()
6928 bool EmulateInstructionARM::EmulateLDRBRegister(const uint32_t opcode, in EmulateLDRBRegister() argument
6942 if (ConditionPassed(opcode)) { in EmulateLDRBRegister()
6956 t = Bits32(opcode, 2, 0); in EmulateLDRBRegister()
6957 n = Bits32(opcode, 5, 3); in EmulateLDRBRegister()
6958 m = Bits32(opcode, 8, 6); in EmulateLDRBRegister()
6972 t = Bits32(opcode, 15, 12); in EmulateLDRBRegister()
6973 n = Bits32(opcode, 19, 16); in EmulateLDRBRegister()
6974 m = Bits32(opcode, 3, 0); in EmulateLDRBRegister()
6983 shift_n = Bits32(opcode, 5, 4); in EmulateLDRBRegister()
6991 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBRegister()
7001 t = Bits32(opcode, 15, 12); in EmulateLDRBRegister()
7002 n = Bits32(opcode, 19, 16); in EmulateLDRBRegister()
7003 m = Bits32(opcode, 3, 0); in EmulateLDRBRegister()
7007 index = BitIsSet(opcode, 24); in EmulateLDRBRegister()
7008 add = BitIsSet(opcode, 23); in EmulateLDRBRegister()
7009 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRBRegister()
7012 uint32_t type = Bits32(opcode, 6, 5); in EmulateLDRBRegister()
7013 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRBRegister()
7090 bool EmulateInstructionARM::EmulateLDRHImmediate(const uint32_t opcode, in EmulateLDRHImmediate() argument
7107 if (ConditionPassed(opcode)) { in EmulateLDRHImmediate()
7119 t = Bits32(opcode, 2, 0); in EmulateLDRHImmediate()
7120 n = Bits32(opcode, 5, 3); in EmulateLDRHImmediate()
7121 imm32 = Bits32(opcode, 10, 6) << 1; in EmulateLDRHImmediate()
7134 t = Bits32(opcode, 15, 12); in EmulateLDRHImmediate()
7135 n = Bits32(opcode, 19, 16); in EmulateLDRHImmediate()
7136 imm32 = Bits32(opcode, 11, 0); in EmulateLDRHImmediate()
7154 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRHImmediate()
7158 t = Bits32(opcode, 15, 12); in EmulateLDRHImmediate()
7159 n = Bits32(opcode, 19, 16); in EmulateLDRHImmediate()
7160 imm32 = Bits32(opcode, 7, 0); in EmulateLDRHImmediate()
7163 index = BitIsSet(opcode, 10); in EmulateLDRHImmediate()
7164 add = BitIsSet(opcode, 9); in EmulateLDRHImmediate()
7165 wback = BitIsSet(opcode, 8); in EmulateLDRHImmediate()
7237 bool EmulateInstructionARM::EmulateLDRHLiteral(const uint32_t opcode, in EmulateLDRHLiteral() argument
7253 if (ConditionPassed(opcode)) { in EmulateLDRHLiteral()
7263 t = Bits32(opcode, 15, 12); in EmulateLDRHLiteral()
7264 imm32 = Bits32(opcode, 11, 0); in EmulateLDRHLiteral()
7265 add = BitIsSet(opcode, 23); in EmulateLDRHLiteral()
7274 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRHLiteral()
7275 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRHLiteral()
7278 t = Bits32(opcode, 15, 12); in EmulateLDRHLiteral()
7280 add = BitIsSet(opcode, 23); in EmulateLDRHLiteral()
7341 bool EmulateInstructionARM::EmulateLDRHRegister(const uint32_t opcode, in EmulateLDRHRegister() argument
7359 if (ConditionPassed(opcode)) { in EmulateLDRHRegister()
7375 t = Bits32(opcode, 2, 0); in EmulateLDRHRegister()
7376 n = Bits32(opcode, 5, 3); in EmulateLDRHRegister()
7377 m = Bits32(opcode, 8, 6); in EmulateLDRHRegister()
7394 t = Bits32(opcode, 15, 12); in EmulateLDRHRegister()
7395 n = Bits32(opcode, 19, 16); in EmulateLDRHRegister()
7396 m = Bits32(opcode, 3, 0); in EmulateLDRHRegister()
7405 shift_n = Bits32(opcode, 5, 4); in EmulateLDRHRegister()
7415 t = Bits32(opcode, 15, 12); in EmulateLDRHRegister()
7416 n = Bits32(opcode, 19, 16); in EmulateLDRHRegister()
7417 m = Bits32(opcode, 3, 0); in EmulateLDRHRegister()
7421 index = BitIsSet(opcode, 24); in EmulateLDRHRegister()
7422 add = BitIsSet(opcode, 23); in EmulateLDRHRegister()
7423 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRHRegister()
7517 bool EmulateInstructionARM::EmulateLDRSBImmediate(const uint32_t opcode, in EmulateLDRSBImmediate() argument
7530 if (ConditionPassed(opcode)) { in EmulateLDRSBImmediate()
7544 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7545 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7546 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSBImmediate()
7564 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRSBImmediate()
7568 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7569 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7570 imm32 = Bits32(opcode, 7, 0); in EmulateLDRSBImmediate()
7573 index = BitIsSet(opcode, 10); in EmulateLDRSBImmediate()
7574 add = BitIsSet(opcode, 9); in EmulateLDRSBImmediate()
7575 wback = BitIsSet(opcode, 8); in EmulateLDRSBImmediate()
7579 ((t == 15) && (BitIsClear(opcode, 10) || BitIsSet(opcode, 9) || in EmulateLDRSBImmediate()
7580 BitIsSet(opcode, 8)))) || in EmulateLDRSBImmediate()
7590 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7591 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7593 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSBImmediate()
7594 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSBImmediate()
7599 index = BitIsSet(opcode, 24); in EmulateLDRSBImmediate()
7600 add = BitIsSet(opcode, 23); in EmulateLDRSBImmediate()
7601 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRSBImmediate()
7666 bool EmulateInstructionARM::EmulateLDRSBLiteral(const uint32_t opcode, in EmulateLDRSBLiteral() argument
7678 if (ConditionPassed(opcode)) { in EmulateLDRSBLiteral()
7688 t = Bits32(opcode, 15, 12); in EmulateLDRSBLiteral()
7689 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSBLiteral()
7690 add = BitIsSet(opcode, 23); in EmulateLDRSBLiteral()
7700 t = Bits32(opcode, 15, 12); in EmulateLDRSBLiteral()
7701 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSBLiteral()
7702 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSBLiteral()
7704 add = BitIsSet(opcode, 23); in EmulateLDRSBLiteral()
7754 bool EmulateInstructionARM::EmulateLDRSBRegister(const uint32_t opcode, in EmulateLDRSBRegister() argument
7768 if (ConditionPassed(opcode)) { in EmulateLDRSBRegister()
7782 t = Bits32(opcode, 2, 0); in EmulateLDRSBRegister()
7783 n = Bits32(opcode, 5, 3); in EmulateLDRSBRegister()
7784 m = Bits32(opcode, 8, 6); in EmulateLDRSBRegister()
7801 t = Bits32(opcode, 15, 12); in EmulateLDRSBRegister()
7802 n = Bits32(opcode, 19, 16); in EmulateLDRSBRegister()
7803 m = Bits32(opcode, 3, 0); in EmulateLDRSBRegister()
7812 shift_n = Bits32(opcode, 5, 4); in EmulateLDRSBRegister()
7822 t = Bits32(opcode, 15, 12); in EmulateLDRSBRegister()
7823 n = Bits32(opcode, 19, 16); in EmulateLDRSBRegister()
7824 m = Bits32(opcode, 3, 0); in EmulateLDRSBRegister()
7828 index = BitIsSet(opcode, 24); in EmulateLDRSBRegister()
7829 add = BitIsSet(opcode, 23); in EmulateLDRSBRegister()
7830 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSBRegister()
7914 bool EmulateInstructionARM::EmulateLDRSHImmediate(const uint32_t opcode, in EmulateLDRSHImmediate() argument
7931 if (ConditionPassed(opcode)) { in EmulateLDRSHImmediate()
7945 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7946 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7947 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSHImmediate()
7966 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRSHImmediate()
7970 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7971 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7972 imm32 = Bits32(opcode, 7, 0); in EmulateLDRSHImmediate()
7975 index = BitIsSet(opcode, 10); in EmulateLDRSHImmediate()
7976 add = BitIsSet(opcode, 9); in EmulateLDRSHImmediate()
7977 wback = BitIsSet(opcode, 8); in EmulateLDRSHImmediate()
7989 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7990 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7991 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSHImmediate()
7992 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSHImmediate()
7997 index = BitIsSet(opcode, 24); in EmulateLDRSHImmediate()
7998 add = BitIsSet(opcode, 23); in EmulateLDRSHImmediate()
7999 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSHImmediate()
8073 bool EmulateInstructionARM::EmulateLDRSHLiteral(const uint32_t opcode, in EmulateLDRSHLiteral() argument
8089 if (ConditionPassed(opcode)) { in EmulateLDRSHLiteral()
8099 t = Bits32(opcode, 15, 12); in EmulateLDRSHLiteral()
8100 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSHLiteral()
8101 add = BitIsSet(opcode, 23); in EmulateLDRSHLiteral()
8111 t = Bits32(opcode, 15, 12); in EmulateLDRSHLiteral()
8112 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSHLiteral()
8113 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSHLiteral()
8115 add = BitIsSet(opcode, 23); in EmulateLDRSHLiteral()
8174 bool EmulateInstructionARM::EmulateLDRSHRegister(const uint32_t opcode, in EmulateLDRSHRegister() argument
8192 if (ConditionPassed(opcode)) { in EmulateLDRSHRegister()
8208 t = Bits32(opcode, 2, 0); in EmulateLDRSHRegister()
8209 n = Bits32(opcode, 5, 3); in EmulateLDRSHRegister()
8210 m = Bits32(opcode, 8, 6); in EmulateLDRSHRegister()
8227 t = Bits32(opcode, 15, 12); in EmulateLDRSHRegister()
8228 n = Bits32(opcode, 19, 16); in EmulateLDRSHRegister()
8229 m = Bits32(opcode, 3, 0); in EmulateLDRSHRegister()
8238 shift_n = Bits32(opcode, 5, 4); in EmulateLDRSHRegister()
8249 t = Bits32(opcode, 15, 12); in EmulateLDRSHRegister()
8250 n = Bits32(opcode, 19, 16); in EmulateLDRSHRegister()
8251 m = Bits32(opcode, 3, 0); in EmulateLDRSHRegister()
8255 index = BitIsSet(opcode, 24); in EmulateLDRSHRegister()
8256 add = BitIsSet(opcode, 23); in EmulateLDRSHRegister()
8257 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSHRegister()
8354 bool EmulateInstructionARM::EmulateSXTB(const uint32_t opcode, in EmulateSXTB() argument
8365 if (ConditionPassed(opcode)) { in EmulateSXTB()
8374 d = Bits32(opcode, 2, 0); in EmulateSXTB()
8375 m = Bits32(opcode, 5, 3); in EmulateSXTB()
8382 d = Bits32(opcode, 11, 8); in EmulateSXTB()
8383 m = Bits32(opcode, 3, 0); in EmulateSXTB()
8384 rotation = Bits32(opcode, 5, 4) << 3; in EmulateSXTB()
8394 d = Bits32(opcode, 15, 12); in EmulateSXTB()
8395 m = Bits32(opcode, 3, 0); in EmulateSXTB()
8396 rotation = Bits32(opcode, 11, 10) << 3; in EmulateSXTB()
8439 bool EmulateInstructionARM::EmulateSXTH(const uint32_t opcode, in EmulateSXTH() argument
8450 if (ConditionPassed(opcode)) { in EmulateSXTH()
8459 d = Bits32(opcode, 2, 0); in EmulateSXTH()
8460 m = Bits32(opcode, 5, 3); in EmulateSXTH()
8467 d = Bits32(opcode, 11, 8); in EmulateSXTH()
8468 m = Bits32(opcode, 3, 0); in EmulateSXTH()
8469 rotation = Bits32(opcode, 5, 4) << 3; in EmulateSXTH()
8479 d = Bits32(opcode, 15, 12); in EmulateSXTH()
8480 m = Bits32(opcode, 3, 0); in EmulateSXTH()
8481 rotation = Bits32(opcode, 11, 10) << 3; in EmulateSXTH()
8524 bool EmulateInstructionARM::EmulateUXTB(const uint32_t opcode, in EmulateUXTB() argument
8535 if (ConditionPassed(opcode)) { in EmulateUXTB()
8544 d = Bits32(opcode, 2, 0); in EmulateUXTB()
8545 m = Bits32(opcode, 5, 3); in EmulateUXTB()
8552 d = Bits32(opcode, 11, 8); in EmulateUXTB()
8553 m = Bits32(opcode, 3, 0); in EmulateUXTB()
8554 rotation = Bits32(opcode, 5, 4) << 3; in EmulateUXTB()
8564 d = Bits32(opcode, 15, 12); in EmulateUXTB()
8565 m = Bits32(opcode, 3, 0); in EmulateUXTB()
8566 rotation = Bits32(opcode, 11, 10) << 3; in EmulateUXTB()
8607 bool EmulateInstructionARM::EmulateUXTH(const uint32_t opcode, in EmulateUXTH() argument
8618 if (ConditionPassed(opcode)) { in EmulateUXTH()
8626 d = Bits32(opcode, 2, 0); in EmulateUXTH()
8627 m = Bits32(opcode, 5, 3); in EmulateUXTH()
8634 d = Bits32(opcode, 11, 8); in EmulateUXTH()
8635 m = Bits32(opcode, 3, 0); in EmulateUXTH()
8636 rotation = Bits32(opcode, 5, 4) << 3; in EmulateUXTH()
8646 d = Bits32(opcode, 15, 12); in EmulateUXTH()
8647 m = Bits32(opcode, 3, 0); in EmulateUXTH()
8648 rotation = Bits32(opcode, 11, 10) << 3; in EmulateUXTH()
8688 bool EmulateInstructionARM::EmulateRFE(const uint32_t opcode, in EmulateRFE() argument
8705 if (ConditionPassed(opcode)) { in EmulateRFE()
8716 n = Bits32(opcode, 19, 16); in EmulateRFE()
8717 wback = BitIsSet(opcode, 21); in EmulateRFE()
8733 n = Bits32(opcode, 19, 16); in EmulateRFE()
8734 wback = BitIsSet(opcode, 21); in EmulateRFE()
8750 n = Bits32(opcode, 19, 16); in EmulateRFE()
8753 wback = BitIsSet(opcode, 21); in EmulateRFE()
8754 increment = BitIsSet(opcode, 23); in EmulateRFE()
8755 wordhigher = (Bit32(opcode, 24) == Bit32(opcode, 23)); in EmulateRFE()
8834 bool EmulateInstructionARM::EmulateEORImm(const uint32_t opcode, in EmulateEORImm() argument
8854 if (ConditionPassed(opcode)) { in EmulateEORImm()
8862 Rd = Bits32(opcode, 11, 8); in EmulateEORImm()
8863 Rn = Bits32(opcode, 19, 16); in EmulateEORImm()
8864 setflags = BitIsSet(opcode, 20); in EmulateEORImm()
8866 opcode, APSR_C, in EmulateEORImm()
8870 return EmulateTEQImm(opcode, eEncodingT1); in EmulateEORImm()
8875 Rd = Bits32(opcode, 15, 12); in EmulateEORImm()
8876 Rn = Bits32(opcode, 19, 16); in EmulateEORImm()
8877 setflags = BitIsSet(opcode, 20); in EmulateEORImm()
8879 ARMExpandImm_C(opcode, APSR_C, in EmulateEORImm()
8885 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateEORImm()
8912 bool EmulateInstructionARM::EmulateEORReg(const uint32_t opcode, in EmulateEORReg() argument
8933 if (ConditionPassed(opcode)) { in EmulateEORReg()
8941 Rd = Rn = Bits32(opcode, 2, 0); in EmulateEORReg()
8942 Rm = Bits32(opcode, 5, 3); in EmulateEORReg()
8948 Rd = Bits32(opcode, 11, 8); in EmulateEORReg()
8949 Rn = Bits32(opcode, 19, 16); in EmulateEORReg()
8950 Rm = Bits32(opcode, 3, 0); in EmulateEORReg()
8951 setflags = BitIsSet(opcode, 20); in EmulateEORReg()
8952 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateEORReg()
8955 return EmulateTEQReg(opcode, eEncodingT1); in EmulateEORReg()
8960 Rd = Bits32(opcode, 15, 12); in EmulateEORReg()
8961 Rn = Bits32(opcode, 19, 16); in EmulateEORReg()
8962 Rm = Bits32(opcode, 3, 0); in EmulateEORReg()
8963 setflags = BitIsSet(opcode, 20); in EmulateEORReg()
8964 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateEORReg()
8969 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateEORReg()
9003 bool EmulateInstructionARM::EmulateORRImm(const uint32_t opcode, in EmulateORRImm() argument
9023 if (ConditionPassed(opcode)) { in EmulateORRImm()
9031 Rd = Bits32(opcode, 11, 8); in EmulateORRImm()
9032 Rn = Bits32(opcode, 19, 16); in EmulateORRImm()
9033 setflags = BitIsSet(opcode, 20); in EmulateORRImm()
9035 opcode, APSR_C, in EmulateORRImm()
9039 return EmulateMOVRdImm(opcode, eEncodingT2); in EmulateORRImm()
9044 Rd = Bits32(opcode, 15, 12); in EmulateORRImm()
9045 Rn = Bits32(opcode, 19, 16); in EmulateORRImm()
9046 setflags = BitIsSet(opcode, 20); in EmulateORRImm()
9048 ARMExpandImm_C(opcode, APSR_C, in EmulateORRImm()
9052 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateORRImm()
9079 bool EmulateInstructionARM::EmulateORRReg(const uint32_t opcode, in EmulateORRReg() argument
9100 if (ConditionPassed(opcode)) { in EmulateORRReg()
9108 Rd = Rn = Bits32(opcode, 2, 0); in EmulateORRReg()
9109 Rm = Bits32(opcode, 5, 3); in EmulateORRReg()
9115 Rd = Bits32(opcode, 11, 8); in EmulateORRReg()
9116 Rn = Bits32(opcode, 19, 16); in EmulateORRReg()
9117 Rm = Bits32(opcode, 3, 0); in EmulateORRReg()
9118 setflags = BitIsSet(opcode, 20); in EmulateORRReg()
9119 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateORRReg()
9122 return EmulateMOVRdRm(opcode, eEncodingT3); in EmulateORRReg()
9127 Rd = Bits32(opcode, 15, 12); in EmulateORRReg()
9128 Rn = Bits32(opcode, 19, 16); in EmulateORRReg()
9129 Rm = Bits32(opcode, 3, 0); in EmulateORRReg()
9130 setflags = BitIsSet(opcode, 20); in EmulateORRReg()
9131 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateORRReg()
9134 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateORRReg()
9168 bool EmulateInstructionARM::EmulateRSBImm(const uint32_t opcode, in EmulateRSBImm() argument
9195 Rd = Bits32(opcode, 2, 0); in EmulateRSBImm()
9196 Rn = Bits32(opcode, 5, 3); in EmulateRSBImm()
9201 Rd = Bits32(opcode, 11, 8); in EmulateRSBImm()
9202 Rn = Bits32(opcode, 19, 16); in EmulateRSBImm()
9203 setflags = BitIsSet(opcode, 20); in EmulateRSBImm()
9204 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateRSBImm()
9209 Rd = Bits32(opcode, 15, 12); in EmulateRSBImm()
9210 Rn = Bits32(opcode, 19, 16); in EmulateRSBImm()
9211 setflags = BitIsSet(opcode, 20); in EmulateRSBImm()
9212 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateRSBImm()
9217 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSBImm()
9240 bool EmulateInstructionARM::EmulateRSBReg(const uint32_t opcode, in EmulateRSBReg() argument
9269 Rd = Bits32(opcode, 11, 8); in EmulateRSBReg()
9270 Rn = Bits32(opcode, 19, 16); in EmulateRSBReg()
9271 Rm = Bits32(opcode, 3, 0); in EmulateRSBReg()
9272 setflags = BitIsSet(opcode, 20); in EmulateRSBReg()
9273 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateRSBReg()
9279 Rd = Bits32(opcode, 15, 12); in EmulateRSBReg()
9280 Rn = Bits32(opcode, 19, 16); in EmulateRSBReg()
9281 Rm = Bits32(opcode, 3, 0); in EmulateRSBReg()
9282 setflags = BitIsSet(opcode, 20); in EmulateRSBReg()
9283 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateRSBReg()
9288 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSBReg()
9319 bool EmulateInstructionARM::EmulateRSCImm(const uint32_t opcode, in EmulateRSCImm() argument
9346 Rd = Bits32(opcode, 15, 12); in EmulateRSCImm()
9347 Rn = Bits32(opcode, 19, 16); in EmulateRSCImm()
9348 setflags = BitIsSet(opcode, 20); in EmulateRSCImm()
9349 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateRSCImm()
9354 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSCImm()
9378 bool EmulateInstructionARM::EmulateRSCReg(const uint32_t opcode, in EmulateRSCReg() argument
9407 Rd = Bits32(opcode, 15, 12); in EmulateRSCReg()
9408 Rn = Bits32(opcode, 19, 16); in EmulateRSCReg()
9409 Rm = Bits32(opcode, 3, 0); in EmulateRSCReg()
9410 setflags = BitIsSet(opcode, 20); in EmulateRSCReg()
9411 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateRSCReg()
9416 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSCReg()
9448 bool EmulateInstructionARM::EmulateSBCImm(const uint32_t opcode, in EmulateSBCImm() argument
9475 Rd = Bits32(opcode, 11, 8); in EmulateSBCImm()
9476 Rn = Bits32(opcode, 19, 16); in EmulateSBCImm()
9477 setflags = BitIsSet(opcode, 20); in EmulateSBCImm()
9478 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSBCImm()
9483 Rd = Bits32(opcode, 15, 12); in EmulateSBCImm()
9484 Rn = Bits32(opcode, 19, 16); in EmulateSBCImm()
9485 setflags = BitIsSet(opcode, 20); in EmulateSBCImm()
9486 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSBCImm()
9491 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSBCImm()
9516 bool EmulateInstructionARM::EmulateSBCReg(const uint32_t opcode, in EmulateSBCReg() argument
9545 Rd = Rn = Bits32(opcode, 2, 0); in EmulateSBCReg()
9546 Rm = Bits32(opcode, 5, 3); in EmulateSBCReg()
9552 Rd = Bits32(opcode, 11, 8); in EmulateSBCReg()
9553 Rn = Bits32(opcode, 19, 16); in EmulateSBCReg()
9554 Rm = Bits32(opcode, 3, 0); in EmulateSBCReg()
9555 setflags = BitIsSet(opcode, 20); in EmulateSBCReg()
9556 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSBCReg()
9561 Rd = Bits32(opcode, 15, 12); in EmulateSBCReg()
9562 Rn = Bits32(opcode, 19, 16); in EmulateSBCReg()
9563 Rm = Bits32(opcode, 3, 0); in EmulateSBCReg()
9564 setflags = BitIsSet(opcode, 20); in EmulateSBCReg()
9565 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSBCReg()
9570 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSBCReg()
9600 bool EmulateInstructionARM::EmulateSUBImmThumb(const uint32_t opcode, in EmulateSUBImmThumb() argument
9624 Rd = Bits32(opcode, 2, 0); in EmulateSUBImmThumb()
9625 Rn = Bits32(opcode, 5, 3); in EmulateSUBImmThumb()
9627 imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32) in EmulateSUBImmThumb()
9630 Rd = Rn = Bits32(opcode, 10, 8); in EmulateSUBImmThumb()
9632 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) in EmulateSUBImmThumb()
9635 Rd = Bits32(opcode, 11, 8); in EmulateSUBImmThumb()
9636 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmThumb()
9637 setflags = BitIsSet(opcode, 20); in EmulateSUBImmThumb()
9638 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSUBImmThumb()
9642 return EmulateCMPImm(opcode, eEncodingT2); in EmulateSUBImmThumb()
9646 return EmulateSUBSPImm(opcode, eEncodingT2); in EmulateSUBImmThumb()
9653 Rd = Bits32(opcode, 11, 8); in EmulateSUBImmThumb()
9654 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmThumb()
9655 setflags = BitIsSet(opcode, 20); in EmulateSUBImmThumb()
9656 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateSUBImmThumb()
9660 return EmulateADR(opcode, eEncodingT2); in EmulateSUBImmThumb()
9664 return EmulateSUBSPImm(opcode, eEncodingT3); in EmulateSUBImmThumb()
9690 bool EmulateInstructionARM::EmulateSUBImmARM(const uint32_t opcode, in EmulateSUBImmARM() argument
9710 if (ConditionPassed(opcode)) { in EmulateSUBImmARM()
9718 Rd = Bits32(opcode, 15, 12); in EmulateSUBImmARM()
9719 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmARM()
9720 setflags = BitIsSet(opcode, 20); in EmulateSUBImmARM()
9721 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBImmARM()
9725 return EmulateADR(opcode, eEncodingA2); in EmulateSUBImmARM()
9729 return EmulateSUBSPImm(opcode, eEncodingA1); in EmulateSUBImmARM()
9734 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBImmARM()
9767 bool EmulateInstructionARM::EmulateTEQImm(const uint32_t opcode, in EmulateTEQImm() argument
9782 if (ConditionPassed(opcode)) { in EmulateTEQImm()
9789 Rn = Bits32(opcode, 19, 16); in EmulateTEQImm()
9791 opcode, APSR_C, in EmulateTEQImm()
9797 Rn = Bits32(opcode, 19, 16); in EmulateTEQImm()
9799 ARMExpandImm_C(opcode, APSR_C, in EmulateTEQImm()
9826 bool EmulateInstructionARM::EmulateTEQReg(const uint32_t opcode, in EmulateTEQReg() argument
9842 if (ConditionPassed(opcode)) { in EmulateTEQReg()
9849 Rn = Bits32(opcode, 19, 16); in EmulateTEQReg()
9850 Rm = Bits32(opcode, 3, 0); in EmulateTEQReg()
9851 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateTEQReg()
9856 Rn = Bits32(opcode, 19, 16); in EmulateTEQReg()
9857 Rm = Bits32(opcode, 3, 0); in EmulateTEQReg()
9858 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateTEQReg()
9892 bool EmulateInstructionARM::EmulateTSTImm(const uint32_t opcode, in EmulateTSTImm() argument
9907 if (ConditionPassed(opcode)) { in EmulateTSTImm()
9914 Rn = Bits32(opcode, 19, 16); in EmulateTSTImm()
9916 opcode, APSR_C, in EmulateTSTImm()
9922 Rn = Bits32(opcode, 19, 16); in EmulateTSTImm()
9924 ARMExpandImm_C(opcode, APSR_C, in EmulateTSTImm()
9951 bool EmulateInstructionARM::EmulateTSTReg(const uint32_t opcode, in EmulateTSTReg() argument
9967 if (ConditionPassed(opcode)) { in EmulateTSTReg()
9974 Rn = Bits32(opcode, 2, 0); in EmulateTSTReg()
9975 Rm = Bits32(opcode, 5, 3); in EmulateTSTReg()
9980 Rn = Bits32(opcode, 19, 16); in EmulateTSTReg()
9981 Rm = Bits32(opcode, 3, 0); in EmulateTSTReg()
9982 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateTSTReg()
9987 Rn = Bits32(opcode, 19, 16); in EmulateTSTReg()
9988 Rm = Bits32(opcode, 3, 0); in EmulateTSTReg()
9989 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateTSTReg()
10021 bool EmulateInstructionARM::EmulateSUBSPReg(const uint32_t opcode, in EmulateSUBSPReg() argument
10041 if (ConditionPassed(opcode)) { in EmulateSUBSPReg()
10051 d = Bits32(opcode, 11, 8); in EmulateSUBSPReg()
10052 m = Bits32(opcode, 3, 0); in EmulateSUBSPReg()
10053 setflags = BitIsSet(opcode, 20); in EmulateSUBSPReg()
10056 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSUBSPReg()
10070 d = Bits32(opcode, 15, 12); in EmulateSUBSPReg()
10071 m = Bits32(opcode, 3, 0); in EmulateSUBSPReg()
10072 setflags = BitIsSet(opcode, 20); in EmulateSUBSPReg()
10077 EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBSPReg()
10080 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBSPReg()
10119 bool EmulateInstructionARM::EmulateADDRegShift(const uint32_t opcode, in EmulateADDRegShift() argument
10137 if (ConditionPassed(opcode)) { in EmulateADDRegShift()
10148 d = Bits32(opcode, 15, 12); in EmulateADDRegShift()
10149 n = Bits32(opcode, 19, 16); in EmulateADDRegShift()
10150 m = Bits32(opcode, 3, 0); in EmulateADDRegShift()
10151 s = Bits32(opcode, 11, 8); in EmulateADDRegShift()
10154 setflags = BitIsSet(opcode, 20); in EmulateADDRegShift()
10155 shift_t = DecodeRegShift(Bits32(opcode, 6, 5)); in EmulateADDRegShift()
10215 bool EmulateInstructionARM::EmulateSUBReg(const uint32_t opcode, in EmulateSUBReg() argument
10235 if (ConditionPassed(opcode)) { in EmulateSUBReg()
10246 d = Bits32(opcode, 2, 0); in EmulateSUBReg()
10247 n = Bits32(opcode, 5, 3); in EmulateSUBReg()
10248 m = Bits32(opcode, 8, 6); in EmulateSUBReg()
10259 d = Bits32(opcode, 11, 8); in EmulateSUBReg()
10260 n = Bits32(opcode, 19, 16); in EmulateSUBReg()
10261 m = Bits32(opcode, 3, 0); in EmulateSUBReg()
10262 setflags = BitIsSet(opcode, 20); in EmulateSUBReg()
10266 return EmulateCMPImm(opcode, eEncodingT3); in EmulateSUBReg()
10270 return EmulateSUBSPReg(opcode, eEncodingT1); in EmulateSUBReg()
10273 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSUBReg()
10277 if ((d == 13) || ((d == 15) && BitIsClear(opcode, 20)) || (n == 15) || in EmulateSUBReg()
10286 d = Bits32(opcode, 15, 12); in EmulateSUBReg()
10287 n = Bits32(opcode, 19, 16); in EmulateSUBReg()
10288 m = Bits32(opcode, 3, 0); in EmulateSUBReg()
10289 setflags = BitIsSet(opcode, 20); in EmulateSUBReg()
10294 EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBReg()
10297 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBReg()
10349 bool EmulateInstructionARM::EmulateSTREX(const uint32_t opcode, in EmulateSTREX() argument
10364 if (ConditionPassed(opcode)) { in EmulateSTREX()
10376 d = Bits32(opcode, 11, 8); in EmulateSTREX()
10377 t = Bits32(opcode, 15, 12); in EmulateSTREX()
10378 n = Bits32(opcode, 19, 16); in EmulateSTREX()
10379 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTREX()
10394 d = Bits32(opcode, 15, 12); in EmulateSTREX()
10395 t = Bits32(opcode, 3, 0); in EmulateSTREX()
10396 n = Bits32(opcode, 19, 16); in EmulateSTREX()
10460 bool EmulateInstructionARM::EmulateSTRBImmARM(const uint32_t opcode, in EmulateSTRBImmARM() argument
10473 if (ConditionPassed(opcode)) { in EmulateSTRBImmARM()
10485 t = Bits32(opcode, 15, 12); in EmulateSTRBImmARM()
10486 n = Bits32(opcode, 19, 16); in EmulateSTRBImmARM()
10487 imm32 = Bits32(opcode, 11, 0); in EmulateSTRBImmARM()
10490 index = BitIsSet(opcode, 24); in EmulateSTRBImmARM()
10491 add = BitIsSet(opcode, 23); in EmulateSTRBImmARM()
10492 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRBImmARM()
10553 bool EmulateInstructionARM::EmulateSTRImmARM(const uint32_t opcode, in EmulateSTRImmARM() argument
10566 if (ConditionPassed(opcode)) { in EmulateSTRImmARM()
10582 t = Bits32(opcode, 15, 12); in EmulateSTRImmARM()
10583 n = Bits32(opcode, 19, 16); in EmulateSTRImmARM()
10584 imm32 = Bits32(opcode, 11, 0); in EmulateSTRImmARM()
10587 index = BitIsSet(opcode, 24); in EmulateSTRImmARM()
10588 add = BitIsSet(opcode, 23); in EmulateSTRImmARM()
10589 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRImmARM()
10662 bool EmulateInstructionARM::EmulateLDRDImmediate(const uint32_t opcode, in EmulateLDRDImmediate() argument
10676 if (ConditionPassed(opcode)) { in EmulateLDRDImmediate()
10691 t = Bits32(opcode, 15, 12); in EmulateLDRDImmediate()
10692 t2 = Bits32(opcode, 11, 8); in EmulateLDRDImmediate()
10693 n = Bits32(opcode, 19, 16); in EmulateLDRDImmediate()
10694 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateLDRDImmediate()
10697 index = BitIsSet(opcode, 24); in EmulateLDRDImmediate()
10698 add = BitIsSet(opcode, 23); in EmulateLDRDImmediate()
10699 wback = BitIsSet(opcode, 21); in EmulateLDRDImmediate()
10716 t = Bits32(opcode, 15, 12); in EmulateLDRDImmediate()
10720 n = Bits32(opcode, 19, 16); in EmulateLDRDImmediate()
10721 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0); in EmulateLDRDImmediate()
10724 index = BitIsSet(opcode, 24); in EmulateLDRDImmediate()
10725 add = BitIsSet(opcode, 23); in EmulateLDRDImmediate()
10726 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRDImmediate()
10729 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateLDRDImmediate()
10810 bool EmulateInstructionARM::EmulateLDRDRegister(const uint32_t opcode, in EmulateLDRDRegister() argument
10824 if (ConditionPassed(opcode)) { in EmulateLDRDRegister()
10837 t = Bits32(opcode, 15, 12); in EmulateLDRDRegister()
10841 n = Bits32(opcode, 19, 16); in EmulateLDRDRegister()
10842 m = Bits32(opcode, 3, 0); in EmulateLDRDRegister()
10845 index = BitIsSet(opcode, 24); in EmulateLDRDRegister()
10846 add = BitIsSet(opcode, 23); in EmulateLDRDRegister()
10847 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRDRegister()
10850 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateLDRDRegister()
10939 bool EmulateInstructionARM::EmulateSTRDImm(const uint32_t opcode, in EmulateSTRDImm() argument
10953 if (ConditionPassed(opcode)) { in EmulateSTRDImm()
10967 t = Bits32(opcode, 15, 12); in EmulateSTRDImm()
10968 t2 = Bits32(opcode, 11, 8); in EmulateSTRDImm()
10969 n = Bits32(opcode, 19, 16); in EmulateSTRDImm()
10970 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTRDImm()
10973 index = BitIsSet(opcode, 24); in EmulateSTRDImm()
10974 add = BitIsSet(opcode, 23); in EmulateSTRDImm()
10975 wback = BitIsSet(opcode, 21); in EmulateSTRDImm()
10991 t = Bits32(opcode, 15, 12); in EmulateSTRDImm()
10996 n = Bits32(opcode, 19, 16); in EmulateSTRDImm()
10997 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0); in EmulateSTRDImm()
11000 index = BitIsSet(opcode, 24); in EmulateSTRDImm()
11001 add = BitIsSet(opcode, 23); in EmulateSTRDImm()
11002 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRDImm()
11005 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateSTRDImm()
11092 bool EmulateInstructionARM::EmulateSTRDReg(const uint32_t opcode, in EmulateSTRDReg() argument
11106 if (ConditionPassed(opcode)) { in EmulateSTRDReg()
11119 t = Bits32(opcode, 15, 12); in EmulateSTRDReg()
11124 n = Bits32(opcode, 19, 16); in EmulateSTRDReg()
11125 m = Bits32(opcode, 3, 0); in EmulateSTRDReg()
11128 index = BitIsSet(opcode, 24); in EmulateSTRDReg()
11129 add = BitIsSet(opcode, 23); in EmulateSTRDReg()
11130 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRDReg()
11133 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateSTRDReg()
11230 bool EmulateInstructionARM::EmulateVLDM(const uint32_t opcode, in EmulateVLDM() argument
11249 if (ConditionPassed(opcode)) { in EmulateVLDM()
11265 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVLDM()
11272 add = BitIsSet(opcode, 23); in EmulateVLDM()
11273 wback = BitIsSet(opcode, 21); in EmulateVLDM()
11276 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLDM()
11277 n = Bits32(opcode, 19, 16); in EmulateVLDM()
11278 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDM()
11281 regs = Bits32(opcode, 7, 0) / 2; in EmulateVLDM()
11300 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVLDM()
11308 add = BitIsSet(opcode, 23); in EmulateVLDM()
11309 wback = BitIsSet(opcode, 21); in EmulateVLDM()
11310 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVLDM()
11311 n = Bits32(opcode, 19, 16); in EmulateVLDM()
11314 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDM()
11315 regs = Bits32(opcode, 7, 0); in EmulateVLDM()
11423 bool EmulateInstructionARM::EmulateVSTM(const uint32_t opcode, in EmulateVSTM() argument
11443 if (ConditionPassed(opcode)) { in EmulateVSTM()
11459 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVSTM()
11466 add = BitIsSet(opcode, 23); in EmulateVSTM()
11467 wback = BitIsSet(opcode, 21); in EmulateVSTM()
11470 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVSTM()
11471 n = Bits32(opcode, 19, 16); in EmulateVSTM()
11472 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTM()
11475 regs = Bits32(opcode, 7, 0) / 2; in EmulateVSTM()
11494 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVSTM()
11502 add = BitIsSet(opcode, 23); in EmulateVSTM()
11503 wback = BitIsSet(opcode, 21); in EmulateVSTM()
11504 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVSTM()
11505 n = Bits32(opcode, 19, 16); in EmulateVSTM()
11508 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTM()
11509 regs = Bits32(opcode, 7, 0); in EmulateVSTM()
11628 bool EmulateInstructionARM::EmulateVLDR(const uint32_t opcode, in EmulateVLDR() argument
11646 if (ConditionPassed(opcode)) { in EmulateVLDR()
11659 add = BitIsSet(opcode, 23); in EmulateVLDR()
11660 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDR()
11663 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLDR()
11664 n = Bits32(opcode, 19, 16); in EmulateVLDR()
11672 add = BitIsSet(opcode, 23); in EmulateVLDR()
11673 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDR()
11676 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVLDR()
11677 n = Bits32(opcode, 19, 16); in EmulateVLDR()
11755 bool EmulateInstructionARM::EmulateVSTR(const uint32_t opcode, in EmulateVSTR() argument
11772 if (ConditionPassed(opcode)) { in EmulateVSTR()
11785 add = BitIsSet(opcode, 23); in EmulateVSTR()
11786 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTR()
11789 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVSTR()
11790 n = Bits32(opcode, 19, 16); in EmulateVSTR()
11802 add = BitIsSet(opcode, 23); in EmulateVSTR()
11803 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTR()
11806 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVSTR()
11807 n = Bits32(opcode, 19, 16); in EmulateVSTR()
11888 bool EmulateInstructionARM::EmulateVLD1Multiple(const uint32_t opcode, in EmulateVLD1Multiple() argument
11903 if (ConditionPassed(opcode)) { in EmulateVLD1Multiple()
11929 uint32_t type = Bits32(opcode, 11, 8); in EmulateVLD1Multiple()
11930 uint32_t align = Bits32(opcode, 5, 4); in EmulateVLD1Multiple()
11960 ebytes = 1 << Bits32(opcode, 7, 6); in EmulateVLD1Multiple()
11965 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1Multiple()
11966 n = Bits32(opcode, 19, 15); in EmulateVLD1Multiple()
11967 m = Bits32(opcode, 3, 0); in EmulateVLD1Multiple()
12046 bool EmulateInstructionARM::EmulateVLD1Single(const uint32_t opcode, in EmulateVLD1Single() argument
12058 if (ConditionPassed(opcode)) { in EmulateVLD1Single()
12072 uint32_t size = Bits32(opcode, 11, 10); in EmulateVLD1Single()
12073 uint32_t index_align = Bits32(opcode, 7, 4); in EmulateVLD1Single()
12076 return EmulateVLD1SingleAll(opcode, encoding); in EmulateVLD1Single()
12131 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1Single()
12132 n = Bits32(opcode, 19, 16); in EmulateVLD1Single()
12133 m = Bits32(opcode, 3, 0); in EmulateVLD1Single()
12223 bool EmulateInstructionARM::EmulateVST1Multiple(const uint32_t opcode, in EmulateVST1Multiple() argument
12238 if (ConditionPassed(opcode)) { in EmulateVST1Multiple()
12253 uint32_t type = Bits32(opcode, 11, 8); in EmulateVST1Multiple()
12254 uint32_t align = Bits32(opcode, 5, 4); in EmulateVST1Multiple()
12289 ebytes = 1 << Bits32(opcode, 7, 6); in EmulateVST1Multiple()
12294 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVST1Multiple()
12295 n = Bits32(opcode, 19, 16); in EmulateVST1Multiple()
12296 m = Bits32(opcode, 3, 0); in EmulateVST1Multiple()
12379 bool EmulateInstructionARM::EmulateVST1Single(const uint32_t opcode, in EmulateVST1Single() argument
12391 if (ConditionPassed(opcode)) { in EmulateVST1Single()
12405 uint32_t size = Bits32(opcode, 11, 10); in EmulateVST1Single()
12406 uint32_t index_align = Bits32(opcode, 7, 4); in EmulateVST1Single()
12465 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVST1Single()
12466 n = Bits32(opcode, 19, 16); in EmulateVST1Single()
12467 m = Bits32(opcode, 3, 0); in EmulateVST1Single()
12538 bool EmulateInstructionARM::EmulateVLD1SingleAll(const uint32_t opcode, in EmulateVLD1SingleAll() argument
12552 if (ConditionPassed(opcode)) { in EmulateVLD1SingleAll()
12567 uint32_t size = Bits32(opcode, 7, 6); in EmulateVLD1SingleAll()
12568 if ((size == 3) || ((size == 0) && BitIsSet(opcode, 4))) in EmulateVLD1SingleAll()
12575 if (BitIsClear(opcode, 5)) in EmulateVLD1SingleAll()
12581 if (BitIsClear(opcode, 4)) in EmulateVLD1SingleAll()
12587 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1SingleAll()
12588 n = Bits32(opcode, 19, 16); in EmulateVLD1SingleAll()
12589 m = Bits32(opcode, 3, 0); in EmulateVLD1SingleAll()
12669 bool EmulateInstructionARM::EmulateSUBSPcLrEtc(const uint32_t opcode, in EmulateSUBSPcLrEtc() argument
12677 case opcode of in EmulateSUBSPcLrEtc()
12696 if (ConditionPassed(opcode)) { in EmulateSUBSPcLrEtc()
12711 imm32 = Bits32(opcode, 7, 0); in EmulateSUBSPcLrEtc()
12723 n = Bits32(opcode, 19, 16); in EmulateSUBSPcLrEtc()
12724 imm32 = ARMExpandImm(opcode); in EmulateSUBSPcLrEtc()
12726 code = Bits32(opcode, 24, 21); in EmulateSUBSPcLrEtc()
12732 n = Bits32(opcode, 19, 16); in EmulateSUBSPcLrEtc()
12733 m = Bits32(opcode, 3, 0); in EmulateSUBSPcLrEtc()
12737 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBSPcLrEtc()
12853 EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, in GetARMOpcodeForInstruction() argument
13233 if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value && in GetARMOpcodeForInstruction()
13241 EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, in GetThumbOpcodeForInstruction() argument
13803 if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value && in GetThumbOpcodeForInstruction()
13925 bool EmulateInstructionARM::ConditionPassed(const uint32_t opcode) { in ConditionPassed() argument
13932 const uint32_t cond = CurrentCond(opcode); in ConditionPassed()
13998 uint32_t EmulateInstructionARM::CurrentCond(const uint32_t opcode) { in CurrentCond() argument
14004 return UnsignedBits(opcode, 31, 28); in CurrentCond()
14012 if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 8) != 0x0f) in CurrentCond()
14013 return Bits32(opcode, 11, 8); in CurrentCond()
14015 if (Bits32(opcode, 31, 27) == 0x1e && Bits32(opcode, 15, 14) == 0x02 && in CurrentCond()
14016 Bits32(opcode, 12, 12) == 0x00 && Bits32(opcode, 25, 22) <= 0x0d) { in CurrentCond()
14017 return Bits32(opcode, 25, 22); in CurrentCond()