Lines Matching refs:getDebugLoc

258         BuildMI(*I.getParent(), I, I.getDebugLoc(),  in selectCopy()
823 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ZextEntryIt->MovOp)) in selectZext()
828 BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectZext()
857 BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectZext()
865 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg) in selectZext()
919 BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectAnyext()
968 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) in selectCmp()
972 MachineInstr &SetInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectCmp()
1028 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) in selectFCmp()
1034 MachineInstr &Set1 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectFCmp()
1036 MachineInstr &Set2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectFCmp()
1038 MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectFCmp()
1062 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) in selectFCmp()
1067 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc), ResultReg); in selectFCmp()
1101 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), X86::EFLAGS) in selectUadde()
1118 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg) in selectUadde()
1122 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg) in selectUadde()
1222 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg) in emitExtractSubreg()
1259 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY)) in emitInsertSubreg()
1337 *BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectUnmergeValues()
1377 MachineInstr &InsertInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectMergeValues()
1389 MachineInstr &CopyInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectMergeValues()
1409 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri)) in selectCondBranch()
1412 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JNE_1)) in selectCondBranch()
1436 const DebugLoc &DbgLoc = I.getDebugLoc(); in materializeFP()
1573 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), in selectShift()
1580 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::KILL), in selectShift()
1585 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg) in selectShift()
1720 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), in selectDivRem()
1726 BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectDivRem()
1730 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0), in selectDivRem()
1737 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), in selectDivRem()
1741 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), in selectDivRem()
1745 BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectDivRem()
1754 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) in selectDivRem()
1769 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg) in selectDivRem()
1773 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri), in selectDivRem()
1779 BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectDivRem()
1786 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), in selectDivRem()
1803 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TRAP)); in selectIntrinsicWSideEffects()