Lines Matching refs:RB
73 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
131 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
173 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
174 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
184 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
404 const RegisterBank &RB, in getLoadStoreOp() argument
413 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
416 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
419 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
421 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
427 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
429 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
514 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp() local
522 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlignment()); in selectLoadStoreOp()