Lines Matching refs:ImplicitOp
742 bool &isKill, MachineOperand &ImplicitOp, in classifyLEAReg() argument
771 ImplicitOp = Src; in classifyLEAReg()
772 ImplicitOp.setImplicit(); in classifyLEAReg()
984 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
986 SrcReg, isKill, ImplicitOp, LV)) in convertToThreeAddress()
997 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
998 MIB.add(ImplicitOp); in convertToThreeAddress()
1017 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1019 ImplicitOp, LV)) in convertToThreeAddress()
1026 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1027 MIB.add(ImplicitOp); in convertToThreeAddress()
1042 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1044 ImplicitOp, LV)) in convertToThreeAddress()
1050 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1051 MIB.add(ImplicitOp); in convertToThreeAddress()
1072 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1074 SrcReg, isKill, ImplicitOp, LV)) in convertToThreeAddress()
1086 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1087 MIB.add(ImplicitOp); in convertToThreeAddress()
1118 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1120 SrcReg, isKill, ImplicitOp, LV)) in convertToThreeAddress()
1126 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1127 MIB.add(ImplicitOp); in convertToThreeAddress()