Lines Matching refs:hasSSE2
103 X86ScalarSSEf64 = Subtarget.hasSSE2(); in X86TargetLowering()
785 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) { in X86TargetLowering()
2074 if (Subtarget.hasSSE2()) in getOptimalMemOpType()
2081 !Subtarget.is64Bit() && Subtarget.hasSSE2()) { in getOptimalMemOpType()
2490 (Subtarget.is64Bit() && !Subtarget.hasSSE2())) { in LowerReturn()
2521 if (!Subtarget.hasSSE2()) in LowerReturn()
3435 else if (Subtarget.hasSSE2()) in LowerFormalArguments()
4998 return Subtarget.hasSSE2(); in hasAndNot()
5304 if (!Subtarget.hasSSE2() && VT.is128BitVector()) { in getZeroVector()
5423 assert(Subtarget.hasSSE2() && "Target assumed to support at least SSE2"); in SplitOpsAndApply()
6868 assert(((VT == MVT::v8i16 && Subtarget.hasSSE2()) || in LowerBuildVectorAsInsert()
8537 if (Subtarget.hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) { in materializeVectorConstant()
12403 if (!Subtarget.hasSSE2()) { in lowerV4F32VectorShuffle()
12444 if (!Subtarget.hasSSE2()) { in lowerV4F32VectorShuffle()
16599 assert(Subtarget.hasSSE2() && "SSE2 required for PINSRW"); in LowerINSERT_VECTOR_ELT()
18120 if (!Subtarget.hasSSE2()) in truncateVectorWithPACK()
19059 (VT == MVT::v4f32 && Subtarget.hasSSE2() && !Reciprocal) || in getSqrtEstimate()
19338 if (!Subtarget.hasSSE2()) in LowerVSETCCWithSUBUS()
19596 assert(Subtarget.hasSSE2() && "Don't know how to lower!"); in LowerVSETCC()
19637 assert(Subtarget.hasSSE2() && !FlipSigns && "Don't know how to lower!"); in LowerVSETCC()
19920 ((Subtarget.hasSSE2() && VT == MVT::f64) || in LowerSELECT()
20308 if (!(VT.is128BitVector() && Subtarget.hasSSE2()) && in LowerEXTEND_VECTOR_INREG()
20558 assert(Subtarget.hasSSE2() && "We only custom lower sext loads with SSE2."); in LowerLoad()
23716 assert(Subtarget.hasSSE2() && !Subtarget.hasSSE41() && in LowerMUL()
23805 assert((VT == MVT::v4i32 && Subtarget.hasSSE2()) || in LowerMULH()
24081 bool LShift = (VT.is128BitVector() && Subtarget.hasSSE2()) || in SupportedVectorShiftWithImm()
24449 assert(Subtarget.hasSSE2() && "Only custom lower when we have SSE2!"); in LowerShift()
25370 assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); in LowerBITCAST()
25400 assert(Subtarget.is64Bit() && !Subtarget.hasSSE2() && in LowerBITCAST()
26369 assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); in ReplaceNodeResults()
26688 assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); in ReplaceNodeResults()
26769 assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); in ReplaceNodeResults()
26932 assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); in ReplaceNodeResults()
30332 SrcVT = DstVT = !Subtarget.hasSSE2() ? MVT::v4f32 : MaskVT; in matchUnaryVectorShuffle()
30370 if (((MaskEltSize == 32) || (MaskEltSize == 64 && Subtarget.hasSSE2())) && in matchUnaryVectorShuffle()
30374 SrcVT = DstVT = !Subtarget.hasSSE2() ? MVT::v4f32 : MaskVT; in matchUnaryVectorShuffle()
30561 if (AllowIntDomain && ((MaskVT.is128BitVector() && Subtarget.hasSSE2()) || in matchUnaryPermuteVectorShuffle()
30591 Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKL : X86ISD::MOVLHPS; in matchBinaryVectorShuffle()
30592 SrcVT = DstVT = Subtarget.hasSSE2() ? MVT::v2f64 : MVT::v4f32; in matchBinaryVectorShuffle()
30597 Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKH : X86ISD::MOVHLPS; in matchBinaryVectorShuffle()
30598 SrcVT = DstVT = Subtarget.hasSSE2() ? MVT::v2f64 : MVT::v4f32; in matchBinaryVectorShuffle()
30601 if (isTargetShuffleEquivalent(Mask, {0, 3}) && Subtarget.hasSSE2() && in matchBinaryVectorShuffle()
30617 if (((MaskVT == MVT::v8i16 || MaskVT == MVT::v16i8) && Subtarget.hasSSE2()) || in matchBinaryVectorShuffle()
30629 (MaskVT.is128BitVector() && Subtarget.hasSSE2()) || in matchBinaryVectorShuffle()
30738 ((MaskVT.is128BitVector() && Subtarget.hasSSE2()) || in matchBinaryPermuteVectorShuffle()
30909 bool AllowIntDomain = (!FloatDomain || (Depth > 3)) && Subtarget.hasSSE2() && in combineX86ShuffleChain()
32908 if (!Subtarget.hasSSE2() || (Subtarget.hasAVX512() && !IsTruncated)) in combineBitcastvxi1()
33286 (Subtarget.hasSSE2() && VT == MVT::f64))) in combineBitcast()
33495 if (!Subtarget.hasSSE2() || Subtarget.hasVLX()) in combineHorizontalPredicateResult()
33567 if (!Subtarget.hasSSE2()) in combineBasicSADPattern()
33726 ((SrcIdx == 0 && Subtarget.hasSSE2()) || Subtarget.hasSSE41())) { in combineExtractWithShuffle()
33732 if ((SrcVT == MVT::v8i16 && Subtarget.hasSSE2()) || in combineExtractWithShuffle()
34100 (Subtarget.hasSSE2() || in combineSelect()
34319 Subtarget.hasSSE2() && VT.getVectorNumElements() >= 2 && in combineSelect()
34386 Subtarget.hasSSE2() && VT.getVectorNumElements() >= 2 && in combineSelect()
35051 if (!Subtarget.hasSSE2()) in reduceVMULWidth()
35258 if (!Subtarget.hasSSE2()) in combineMulToPMADDWD()
35307 if (!Subtarget.hasSSE2()) in combineMulToPMULDQ()
35905 if (Subtarget.hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { in combineCompareEqual()
36119 (Subtarget.hasSSE2() && VT == MVT::i64))) { in convertIntLogicToFPLogic()
36360 if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32) { in combineAnd()
36499 if (!((VT.is128BitVector() && Subtarget.hasSSE2()) || in combineLogicBlendIntoPBLENDV()
36700 if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32) { in combineOr()
36912 case MVT::v4i32: if (!Subtarget.hasSSE2()) return SDValue(); break; in foldVectorXorShiftIntoCmp()
37151 if (!Subtarget.hasSSE2()) in detectAVGPattern()
37880 !Subtarget.useSoftFloat() && !NoImplicitFloatOps && Subtarget.hasSSE2(); in combineStore()
38271 if (!Subtarget.hasSSE2() || Subtarget.hasAVX2()) in combineVectorTruncation()
38306 if (!Subtarget.hasSSE2() || Subtarget.hasAVX512()) in combineVectorSignBitsTruncation()
38363 if (!Subtarget.hasSSE2()) in combinePMULH()
38712 if (!VT.isVector() || !Subtarget.hasSSE2()) in lowerX86FPLogicOp()
38756 if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && in combineXor()
38841 (VT == MVT::f64 && Subtarget.hasSSE2()) || in combineFAndFNotToFAndn()
38842 (VT == MVT::v4f32 && Subtarget.hasSSE1() && !Subtarget.hasSSE2()))) in combineFAndFNotToFAndn()
38944 (Subtarget.hasSSE2() && (VT == MVT::f64 || VT == MVT::v2f64)) || in combineFMinNumFMaxNum()
39265 if (!Subtarget.hasSSE2() || Subtarget.hasAVX512()) in combineToExtendBoolVectorInReg()
39357 if (!Subtarget.hasSSE2()) in combineToExtendVectorInReg()
39759 if ((OpSize == 128 && Subtarget.hasSSE2()) || in combineVectorSizedSetCCEquality()
39878 if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32 && in combineSetCC()
40561 if (!Subtarget.hasSSE2()) in combineLoopMAddPattern()
40621 if (!Subtarget.hasSSE2()) in combineLoopSADPattern()
40737 if (!Subtarget.hasSSE2()) in matchPMADDWD()
40835 if (!Subtarget.hasSSE2()) in combineAddToSUBUS()
40871 if (!Subtarget.hasSSE2()) in matchPMADDWD_2()
41034 if (!(Subtarget.hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) && in combineSubToSubus()
42040 if (!Subtarget.hasSSE2()) in getSingleConstraintMatchWeight()
42128 if (Subtarget.hasSSE2()) in LowerXConstraint()
42408 if (!Subtarget.hasSSE2()) break; in getRegForInlineAsmConstraint()