Lines Matching refs:ValLoc
2367 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc, in lowerMasksToReg() argument
2372 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg, in lowerMasksToReg()
2375 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) || in lowerMasksToReg()
2376 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) { in lowerMasksToReg()
2382 if (ValLoc == MVT::i32) in lowerMasksToReg()
2383 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy); in lowerMasksToReg()
2387 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) || in lowerMasksToReg()
2388 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) { in lowerMasksToReg()
2391 return DAG.getBitcast(ValLoc, ValArg); in lowerMasksToReg()
2394 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg); in lowerMasksToReg()
2745 const EVT &ValLoc, const SDLoc &Dl, in lowerRegToMasks() argument
2754 assert(ValLoc == MVT::i64 && "Expecting only i64 locations"); in lowerRegToMasks()