6670   case X86ISD::PACKUS: {  in getFauxShuffleMask()
10140         PackOpcode = X86ISD::PACKUS;  in matchVectorShuffleWithPACK()
13597     SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);  in lowerV16I8VectorShuffle()
13600       Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);  in lowerV16I8VectorShuffle()
13657   return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);  in lowerV16I8VectorShuffle()
18115   assert((Opcode == X86ISD::PACKSS || Opcode == X86ISD::PACKUS) &&  in truncateVectorWithPACK()
18327             truncateVectorWithPACK(X86ISD::PACKUS, VT, In, DL, DAG, Subtarget))  in LowerTRUNCATE()
18410     return DAG.getNode(X86ISD::PACKUS, DL, VT, InLo, InHi);  in LowerTRUNCATE()
23711     return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);  in LowerMUL()
24011   return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);  in LowerMULH()
24425       return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);  in convertShiftLeftToScale()
24717     return DAG.getNode(X86ISD::PACKUS, dl, VT, LoR, HiR);  in LowerShift()
24824       return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);  in LowerShift()
24843     return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);  in LowerShift()
25466     V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,  in LowerHorizontalByteSum()
27245   case X86ISD::PACKUS:             return "X86ISD::PACKUS";  in getTargetNodeName()
30139   case X86ISD::PACKUS: {  in computeKnownBitsForTargetNode()
31768          Opcode0 == X86ISD::PACKSS || Opcode0 == X86ISD::PACKUS)) {  in combineTargetShuffle()
32488   case X86ISD::PACKUS: {  in SimplifyDemandedVectorEltsForTargetNode()
35674   assert((X86ISD::PACKSS == Opcode || X86ISD::PACKUS == Opcode) &&  in combineVectorPack()
37116           return truncateVectorWithPACK(X86ISD::PACKUS, VT, Mid, DL, DAG,  in combineTruncateWithSat()
37119         return truncateVectorWithPACK(X86ISD::PACKUS, VT, USatVal, DL, DAG,  in combineTruncateWithSat()
38235   return truncateVectorWithPACK(X86ISD::PACKUS, OutVT, In, DL, DAG, Subtarget);  in combineVectorTruncationWithPACKUS()
38338     return truncateVectorWithPACK(X86ISD::PACKUS, VT, In, DL, DAG, Subtarget);  in combineVectorSignBitsTruncation()
41563   case X86ISD::PACKUS:      return combineVectorPack(N, DAG, DCI, Subtarget);  in PerformDAGCombine()