Lines Matching refs:PACKSS
6669 case X86ISD::PACKSS: in getFauxShuffleMask()
6679 if (Opcode == X86ISD::PACKSS) { in getFauxShuffleMask()
10149 PackOpcode = X86ISD::PACKSS; in matchVectorShuffleWithPACK()
18115 assert((Opcode == X86ISD::PACKSS || Opcode == X86ISD::PACKUS) && in truncateVectorWithPACK()
18150 (Opcode == X86ISD::PACKSS || Subtarget.hasSSE41())) { in truncateVectorWithPACK()
18334 truncateVectorWithPACK(X86ISD::PACKSS, VT, In, DL, DAG, Subtarget)) in LowerTRUNCATE()
27244 case X86ISD::PACKSS: return "X86ISD::PACKSS"; in getTargetNodeName()
30251 case X86ISD::PACKSS: { in ComputeNumSignBitsForTargetNode()
31768 Opcode0 == X86ISD::PACKSS || Opcode0 == X86ISD::PACKUS)) { in combineTargetShuffle()
32487 case X86ISD::PACKSS: in SimplifyDemandedVectorEltsForTargetNode()
32987 V = DAG.getNode(X86ISD::PACKSS, DL, MVT::v16i8, V, in combineBitcastvxi1()
35674 assert((X86ISD::PACKSS == Opcode || X86ISD::PACKUS == Opcode) && in combineVectorPack()
35686 bool IsSigned = (X86ISD::PACKSS == Opcode); in combineVectorPack()
37113 SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL, in combineTruncateWithSat()
37123 return truncateVectorWithPACK(X86ISD::PACKSS, VT, SSatVal, DL, DAG, in combineTruncateWithSat()
38247 return truncateVectorWithPACK(X86ISD::PACKSS, OutVT, In, DL, DAG, Subtarget); in combineVectorTruncationWithPACKSS()
38344 return truncateVectorWithPACK(X86ISD::PACKSS, VT, In, DL, DAG, Subtarget); in combineVectorSignBitsTruncation()
41562 case X86ISD::PACKSS: in PerformDAGCombine()