Lines Matching refs:OpVT
5450 EVT OpVT = Op.getValueType(); in SplitOpsAndApply() local
5451 unsigned NumSubElts = OpVT.getVectorNumElements() / NumSubs; in SplitOpsAndApply()
5452 unsigned SizeSub = OpVT.getSizeInBits() / NumSubs; in SplitOpsAndApply()
5493 MVT OpVT = Op.getSimpleValueType(); in insert1BitVector() local
5494 unsigned NumElems = OpVT.getVectorNumElements(); in insert1BitVector()
5499 MVT WideOpVT = OpVT; in insert1BitVector()
5510 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx); in insert1BitVector()
5534 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx); in insert1BitVector()
5544 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
5557 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
5581 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx); in insert1BitVector()
5606 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx); in insert1BitVector()
16655 MVT OpVT = Op.getSimpleValueType(); in LowerSCALAR_TO_VECTOR() local
16660 return getZeroVector(OpVT, Subtarget, DAG, dl); in LowerSCALAR_TO_VECTOR()
16664 if (!OpVT.is128BitVector()) { in LowerSCALAR_TO_VECTOR()
16666 unsigned SizeFactor = OpVT.getSizeInBits() / 128; in LowerSCALAR_TO_VECTOR()
16667 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(), in LowerSCALAR_TO_VECTOR()
16668 OpVT.getVectorNumElements() / SizeFactor); in LowerSCALAR_TO_VECTOR()
16673 return insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); in LowerSCALAR_TO_VECTOR()
16675 assert(OpVT.is128BitVector() && "Expected an SSE type!"); in LowerSCALAR_TO_VECTOR()
16678 if (OpVT == MVT::v4i32) in LowerSCALAR_TO_VECTOR()
16683 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt)); in LowerSCALAR_TO_VECTOR()
18724 MVT OpVT = N0.getSimpleValueType(); in LowerFGETSIGN() local
18725 assert((OpVT == MVT::f32 || OpVT == MVT::f64) && in LowerFGETSIGN()
18729 MVT VecVT = (OpVT == MVT::f32 ? MVT::v4f32 : MVT::v2f64); in LowerFGETSIGN()
23410 MVT OpVT = VT; in LowerCTLZ() local
23421 OpVT = MVT::i32; in LowerCTLZ()
23422 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); in LowerCTLZ()
23426 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); in LowerCTLZ()
23433 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT), in LowerCTLZ()
23437 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops); in LowerCTLZ()
23441 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, in LowerCTLZ()
23442 DAG.getConstant(NumBits - 1, dl, OpVT)); in LowerCTLZ()
39735 EVT OpVT = X.getValueType(); in combineVectorSizedSetCCEquality() local
39736 unsigned OpSize = OpVT.getSizeInBits(); in combineVectorSizedSetCCEquality()
39737 if (!OpVT.isScalarInteger() || OpSize < 128) in combineVectorSizedSetCCEquality()
39808 EVT OpVT = LHS.getValueType(); in combineSetCC() local
39816 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, RHS, LHS.getOperand(1)); in combineSetCC()
39817 return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC); in combineSetCC()
39823 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1)); in combineSetCC()
39824 return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC); in combineSetCC()
39869 (OpVT.getVectorElementType() == MVT::i8 || in combineSetCC()
39870 OpVT.getVectorElementType() == MVT::i16)) { in combineSetCC()
39871 SDValue Setcc = DAG.getNode(ISD::SETCC, DL, OpVT, LHS, RHS, in combineSetCC()
41182 MVT OpVT = N->getSimpleValueType(0); in combineInsertSubvector() local
41184 bool IsI1Vector = OpVT.getVectorElementType() == MVT::i1; in combineInsertSubvector()
41196 return getZeroVector(OpVT, Subtarget, DAG, dl); in combineInsertSubvector()
41203 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineInsertSubvector()
41204 getZeroVector(OpVT, Subtarget, DAG, dl), in combineInsertSubvector()
41220 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineInsertSubvector()
41221 getZeroVector(OpVT, Subtarget, DAG, dl), in combineInsertSubvector()
41231 unsigned NumElems = OpVT.getSizeInBits() / CastVT.getScalarSizeInBits(); in combineInsertSubvector()
41236 return DAG.getBitcast(OpVT, Insert); in combineInsertSubvector()
41247 SubVec.getOperand(0).getSimpleValueType() == OpVT && in combineInsertSubvector()
41251 int VecNumElts = OpVT.getVectorNumElements(); in combineInsertSubvector()
41261 return DAG.getVectorShuffle(OpVT, dl, Vec, SubVec.getOperand(0), Mask); in combineInsertSubvector()
41282 if ((IdxVal == OpVT.getVectorNumElements() / 2) && in combineInsertSubvector()
41284 OpVT.getSizeInBits() == SubVecVT.getSizeInBits() * 2) { in combineInsertSubvector()
41294 OpVT, AS, Alignment, &Fast) && Fast) { in combineInsertSubvector()
41296 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, in combineInsertSubvector()
41305 return DAG.getNode(X86ISD::SUBV_BROADCAST, dl, OpVT, SubVec); in combineInsertSubvector()
41310 return DAG.getNode(X86ISD::SUBV_BROADCAST, dl, OpVT, in combineInsertSubvector()
41317 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineInsertSubvector()
41318 getZeroVector(OpVT, Subtarget, DAG, dl), SubVec2, in combineInsertSubvector()
41326 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, DAG.getUNDEF(OpVT), in combineInsertSubvector()
41328 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Vec, SubVec, in combineInsertSubvector()
41377 MVT OpVT = N->getSimpleValueType(0); in combineExtractSubvector() local
41382 return getZeroVector(OpVT, Subtarget, DAG, SDLoc(N)); in combineExtractSubvector()
41385 if (OpVT.getScalarType() == MVT::i1) in combineExtractSubvector()
41386 return DAG.getConstant(1, SDLoc(N), OpVT); in combineExtractSubvector()
41387 return getOnesVector(OpVT, DAG, SDLoc(N)); in combineExtractSubvector()
41392 OpVT, SDLoc(N), in combineExtractSubvector()
41393 InVec.getNode()->ops().slice(IdxVal, OpVT.getVectorNumElements())); in combineExtractSubvector()
41399 if (OpVT == MVT::v2f64 && InVec.getValueType() == MVT::v4f64) { in combineExtractSubvector()
41403 return DAG.getNode(X86ISD::CVTSI2P, SDLoc(N), OpVT, InVec.getOperand(0)); in combineExtractSubvector()
41408 return DAG.getNode(X86ISD::VFPEXT, SDLoc(N), OpVT, InVec.getOperand(0)); in combineExtractSubvector()
41412 OpVT.is128BitVector() && in combineExtractSubvector()
41417 return DAG.getNode(ExtOp, SDLoc(N), OpVT, InVec.getOperand(0)); in combineExtractSubvector()
41421 OpVT.is128BitVector() && in combineExtractSubvector()
41423 return DAG.getNode(InOpcode, SDLoc(N), OpVT, InVec.getOperand(0)); in combineExtractSubvector()
41428 if (InVecBC.getOpcode() == X86ISD::PSHUFB && OpVT.is128BitVector()) { in combineExtractSubvector()
41434 return DAG.getBitcast(OpVT, SubPSHUFB); in combineExtractSubvector()