Lines Matching refs:LogicVT
18623 MVT LogicVT = VT; in LowerFABSorFNEG() local
18625 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32; in LowerFABSorFNEG()
18632 SDValue Mask = DAG.getConstantFP(APFloat(Sem, MaskElt), dl, LogicVT); in LowerFABSorFNEG()
18642 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
18646 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand); in LowerFABSorFNEG()
18647 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
18682 MVT LogicVT = VT; in LowerFCOPYSIGN() local
18684 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32; in LowerFCOPYSIGN()
18689 APFloat(Sem, APInt::getSignMask(EltSizeInBits)), dl, LogicVT); in LowerFCOPYSIGN()
18691 APFloat(Sem, APInt::getSignedMaxValue(EltSizeInBits)), dl, LogicVT); in LowerFCOPYSIGN()
18695 Sign = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Sign); in LowerFCOPYSIGN()
18696 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Sign, SignMask); in LowerFCOPYSIGN()
18705 MagBits = DAG.getConstantFP(APF, dl, LogicVT); in LowerFCOPYSIGN()
18709 Mag = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Mag); in LowerFCOPYSIGN()
18710 MagBits = DAG.getNode(X86ISD::FAND, dl, LogicVT, Mag, MagMask); in LowerFCOPYSIGN()
18714 SDValue Or = DAG.getNode(X86ISD::FOR, dl, LogicVT, MagBits, SignBit); in LowerFCOPYSIGN()