Lines Matching refs:IntVT
3440 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32; in LowerFormalArguments() local
3441 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
4891 bool X86TargetLowering::shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, in shouldUseStrictFP_TO_INT() argument
33008 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), Imm.getBitWidth()); in combinevXi1ConstantToInteger() local
33009 return DAG.getConstant(Imm, SDLoc(Op), IntVT); in combinevXi1ConstantToInteger()
35972 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32; in combineCompareEqual() local
35985 IntVT = MVT::i32; in combineCompareEqual()
35988 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF); in combineCompareEqual()
35989 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI, in combineCompareEqual()
35990 DAG.getConstant(1, DL, IntVT)); in combineCompareEqual()
38719 MVT IntVT = MVT::getVectorVT(IntSVT, VT.getSizeInBits() / IntBits); in lowerX86FPLogicOp() local
38721 SDValue Op0 = DAG.getBitcast(IntVT, N->getOperand(0)); in lowerX86FPLogicOp()
38722 SDValue Op1 = DAG.getBitcast(IntVT, N->getOperand(1)); in lowerX86FPLogicOp()
38731 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1); in lowerX86FPLogicOp()
40090 EVT IntVT = BV->getValueType(0); in combineVectorCompareAndMaskUnaryOp() local
40095 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst); in combineVectorCompareAndMaskUnaryOp()
40096 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in combineVectorCompareAndMaskUnaryOp()