Lines Matching refs:ExtVT
11211 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale), in lowerVectorShuffleAsSpecificZeroOrAnyExtend() local
11214 InputV = getExtendInVec(/*Signed*/false, DL, ExtVT, InputV, DAG); in lowerVectorShuffleAsSpecificZeroOrAnyExtend()
11489 MVT ExtVT = VT; in lowerVectorShuffleAsElementInsertion() local
11519 ExtVT = MVT::getVectorVT(MVT::i32, ExtVT.getSizeInBits() / 32); in lowerVectorShuffleAsElementInsertion()
11522 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S); in lowerVectorShuffleAsElementInsertion()
11534 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!"); in lowerVectorShuffleAsElementInsertion()
11548 ExtVT, V1, V2); in lowerVectorShuffleAsElementInsertion()
11555 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2); in lowerVectorShuffleAsElementInsertion()
11556 if (ExtVT != VT) in lowerVectorShuffleAsElementInsertion()
11837 MVT ExtVT = MVT::getVectorVT(SrcVT.getScalarType(), in lowerVectorShuffleAsBroadcast() local
11840 V = DAG.getBitcast(ExtVT, V); in lowerVectorShuffleAsBroadcast()
15905 MVT ExtVT; in lower1BitVectorShuffle() local
15910 ExtVT = MVT::v2i64; in lower1BitVectorShuffle()
15913 ExtVT = MVT::v4i32; in lower1BitVectorShuffle()
15918 ExtVT = Subtarget.hasVLX() ? MVT::v8i32 : MVT::v8i64; in lower1BitVectorShuffle()
15923 ExtVT = Subtarget.canExtendTo512DQ() ? MVT::v16i32 : MVT::v16i16; in lower1BitVectorShuffle()
15929 ExtVT = Subtarget.canExtendTo512BW() ? MVT::v32i16 : MVT::v32i8; in lower1BitVectorShuffle()
15932 ExtVT = MVT::v64i8; in lower1BitVectorShuffle()
15936 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1); in lower1BitVectorShuffle()
15937 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2); in lower1BitVectorShuffle()
15939 SDValue Shuffle = DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask); in lower1BitVectorShuffle()
15944 return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, ExtVT), in lower1BitVectorShuffle()
18056 MVT ExtVT = VT; in LowerZERO_EXTEND_Mask() local
18062 ExtVT = MVT::getVectorVT(MVT::i32, NumElts); in LowerZERO_EXTEND_Mask()
18066 MVT WideVT = ExtVT; in LowerZERO_EXTEND_Mask()
18067 if (!ExtVT.is512BitVector() && !Subtarget.hasVLX()) { in LowerZERO_EXTEND_Mask()
18068 NumElts *= 512 / ExtVT.getSizeInBits(); in LowerZERO_EXTEND_Mask()
18072 WideVT = MVT::getVectorVT(ExtVT.getVectorElementType(), in LowerZERO_EXTEND_Mask()
18082 if (VT != ExtVT) { in LowerZERO_EXTEND_Mask()
18232 MVT ExtVT = MVT::getVectorVT(MVT::i16, InVT.getSizeInBits()/16); in LowerTruncateVecI1() local
18233 In = DAG.getNode(ISD::SHL, DL, ExtVT, in LowerTruncateVecI1()
18234 DAG.getBitcast(ExtVT, In), in LowerTruncateVecI1()
18235 DAG.getConstant(ShiftInx, DL, ExtVT)); in LowerTruncateVecI1()
18273 MVT ExtVT = MVT::getVectorVT(EltVT, NumElts); in LowerTruncateVecI1() local
18274 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In); in LowerTruncateVecI1()
18275 InVT = ExtVT; in LowerTruncateVecI1()
20233 MVT ExtVT = VT; in LowerSIGN_EXTEND_Mask() local
20239 ExtVT = MVT::getVectorVT(MVT::i32, NumElts); in LowerSIGN_EXTEND_Mask()
20243 MVT WideVT = ExtVT; in LowerSIGN_EXTEND_Mask()
20244 if (!ExtVT.is512BitVector() && !Subtarget.hasVLX()) { in LowerSIGN_EXTEND_Mask()
20245 NumElts *= 512 / ExtVT.getSizeInBits(); in LowerSIGN_EXTEND_Mask()
20249 WideVT = MVT::getVectorVT(ExtVT.getVectorElementType(), NumElts); in LowerSIGN_EXTEND_Mask()
20264 if (VT != ExtVT) { in LowerSIGN_EXTEND_Mask()
24312 MVT ExtVT = MVT::getVectorVT(MVT::i16, NumElts / 2); in LowerScalarVariableShift() local
24313 if (SupportedVectorShiftWithBaseAmnt(ExtVT, Subtarget, Opcode)) { in LowerScalarVariableShift()
24320 SDValue BitMask = DAG.getConstant(-1, dl, ExtVT); in LowerScalarVariableShift()
24321 BitMask = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, BitMask, in LowerScalarVariableShift()
24324 BitMask = getTargetVShiftByConstNode(LogicalX86Op, dl, ExtVT, BitMask, in LowerScalarVariableShift()
24330 SDValue Res = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, in LowerScalarVariableShift()
24331 DAG.getBitcast(ExtVT, R), BaseShAmt, in LowerScalarVariableShift()
24339 SDValue SignMask = DAG.getConstant(0x8080, dl, ExtVT); in LowerScalarVariableShift()
24340 SignMask = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, SignMask, in LowerScalarVariableShift()
24663 MVT ExtVT = MVT::getVectorVT(EvtSVT, VT.getVectorNumElements()); in LowerShift() local
24665 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
24666 Amt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Amt); in LowerShift()
24668 DAG.getNode(Opc, dl, ExtVT, R, Amt)); in LowerShift()
24723 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2); in LowerShift() local
24756 Amt = DAG.getBitcast(ExtVT, Amt); in LowerShift()
24757 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ExtVT, Amt, 5, DAG); in LowerShift()
24789 ALo = DAG.getBitcast(ExtVT, ALo); in LowerShift()
24790 AHi = DAG.getBitcast(ExtVT, AHi); in LowerShift()
24791 RLo = DAG.getBitcast(ExtVT, RLo); in LowerShift()
24792 RHi = DAG.getBitcast(ExtVT, RHi); in LowerShift()
24795 SDValue MLo = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RLo, 4, DAG); in LowerShift()
24796 SDValue MHi = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RHi, 4, DAG); in LowerShift()
24797 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift()
24798 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi); in LowerShift()
24801 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo); in LowerShift()
24802 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi); in LowerShift()
24805 MLo = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RLo, 2, DAG); in LowerShift()
24806 MHi = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RHi, 2, DAG); in LowerShift()
24807 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift()
24808 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi); in LowerShift()
24811 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo); in LowerShift()
24812 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi); in LowerShift()
24815 MLo = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RLo, 1, DAG); in LowerShift()
24816 MHi = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RHi, 1, DAG); in LowerShift()
24817 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift()
24818 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi); in LowerShift()
24822 RLo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, RLo, 8, DAG); in LowerShift()
24823 RHi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, RHi, 8, DAG); in LowerShift()
24829 MVT ExtVT = MVT::v8i32; in LowerShift() local
24835 ALo = DAG.getBitcast(ExtVT, ALo); in LowerShift()
24836 AHi = DAG.getBitcast(ExtVT, AHi); in LowerShift()
24837 RLo = DAG.getBitcast(ExtVT, RLo); in LowerShift()
24838 RHi = DAG.getBitcast(ExtVT, RHi); in LowerShift()
24839 SDValue Lo = DAG.getNode(Opc, dl, ExtVT, RLo, ALo); in LowerShift()
24840 SDValue Hi = DAG.getNode(Opc, dl, ExtVT, RHi, AHi); in LowerShift()
24841 Lo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, Lo, 16, DAG); in LowerShift()
24842 Hi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, Hi, 16, DAG); in LowerShift()
24856 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2); in LowerShift() local
24857 V0 = DAG.getBitcast(ExtVT, V0); in LowerShift()
24858 V1 = DAG.getBitcast(ExtVT, V1); in LowerShift()
24859 Sel = DAG.getBitcast(ExtVT, Sel); in LowerShift()
24860 return DAG.getBitcast(VT, DAG.getSelect(dl, ExtVT, Sel, V0, V1)); in LowerShift()
25000 MVT ExtVT = MVT::getVectorVT(MVT::i16, NumElts / 2); in LowerRotate() local
25022 Amt = DAG.getBitcast(ExtVT, Amt); in LowerRotate()
25023 Amt = DAG.getNode(ISD::SHL, DL, ExtVT, Amt, DAG.getConstant(5, DL, ExtVT)); in LowerRotate()