216 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,  in getRegOperandNumElts()  function
525       DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0),  in EmitAnyX86InstComments()
541       DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),  in EmitAnyX86InstComments()
557       DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0),  in EmitAnyX86InstComments()
571       DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),  in EmitAnyX86InstComments()
649     DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);  in EmitAnyX86InstComments()
658     DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);  in EmitAnyX86InstComments()
667     DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask);  in EmitAnyX86InstComments()
683       DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0),  in EmitAnyX86InstComments()
701       DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0),  in EmitAnyX86InstComments()
715       DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0),  in EmitAnyX86InstComments()
733       DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0),  in EmitAnyX86InstComments()
751       DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0),  in EmitAnyX86InstComments()
763       DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,  in EmitAnyX86InstComments()
775       DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0),  in EmitAnyX86InstComments()
787       DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0),  in EmitAnyX86InstComments()
822     DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);  in EmitAnyX86InstComments()
835     DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);  in EmitAnyX86InstComments()
848     DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);  in EmitAnyX86InstComments()
859     DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);  in EmitAnyX86InstComments()
872     DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);  in EmitAnyX86InstComments()
885     DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);  in EmitAnyX86InstComments()
898     DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);  in EmitAnyX86InstComments()
909     DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);  in EmitAnyX86InstComments()
919       DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64,  in EmitAnyX86InstComments()
932       DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32,  in EmitAnyX86InstComments()
945     decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64,  in EmitAnyX86InstComments()
958     decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32,  in EmitAnyX86InstComments()
971     DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);  in EmitAnyX86InstComments()
982     DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);  in EmitAnyX86InstComments()
993     DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);  in EmitAnyX86InstComments()
1004     DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);  in EmitAnyX86InstComments()
1015       DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,  in EmitAnyX86InstComments()
1027       DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64,  in EmitAnyX86InstComments()
1054       DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),  in EmitAnyX86InstComments()
1066       DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),  in EmitAnyX86InstComments()
1206     DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), ShuffleMask);  in EmitAnyX86InstComments()
1214     DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask);  in EmitAnyX86InstComments()
1222     DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);  in EmitAnyX86InstComments()
1230     DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask);  in EmitAnyX86InstComments()
1238     DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);  in EmitAnyX86InstComments()
1246     DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);  in EmitAnyX86InstComments()