Lines Matching refs:bits
66 bits<5> AccessBytes = 0;
71 bits<4> CCValues = 0;
75 bits<4> CompareZeroCCMask = 0;
148 // bits<4> Rn : register input or output for operand n
149 // bits<5> Vn : vector register input or output for operand n
150 // bits<m> In : immediate value of width m for operand n
151 // bits<4> BDn : address operand n, which has a base and a displacement
152 // bits<m> XBDn : address operand n, which has an index, a base and a
154 // bits<m> VBDn : address operand n, which has a vector index, a base and a
156 // bits<4> Xn : index register for address operand n
157 // bits<4> Mn : mode value for operand n
165 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
167 field bits<16> Inst;
168 field bits<16> SoftFail = 0;
173 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
175 field bits<16> Inst;
176 field bits<16> SoftFail = 0;
178 bits<8> I1;
184 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
186 field bits<32> Inst;
187 field bits<32> SoftFail = 0;
189 bits<4> I1;
190 bits<4> I2;
198 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
200 field bits<48> Inst;
201 field bits<48> SoftFail = 0;
203 bits<4> M1;
204 bits<12> RI2;
205 bits<24> RI3;
213 class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
215 field bits<32> Inst;
216 field bits<32> SoftFail = 0;
218 bits<4> R1;
219 bits<16> I2;
227 class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
229 field bits<32> Inst;
230 field bits<32> SoftFail = 0;
232 bits<4> R1;
233 bits<16> RI2;
241 class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
243 field bits<32> Inst;
244 field bits<32> SoftFail = 0;
246 bits<4> M1;
247 bits<16> RI2;
255 class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
257 field bits<48> Inst;
258 field bits<48> SoftFail = 0;
260 bits<4> R1;
261 bits<16> I2;
262 bits<4> M3;
273 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
275 field bits<48> Inst;
276 field bits<48> SoftFail = 0;
278 bits<4> R1;
279 bits<4> R2;
280 bits<4> M3;
281 bits<16> RI4;
292 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
294 field bits<48> Inst;
295 field bits<48> SoftFail = 0;
297 bits<4> R1;
298 bits<8> I2;
299 bits<4> M3;
300 bits<16> RI4;
310 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
312 field bits<48> Inst;
313 field bits<48> SoftFail = 0;
315 bits<4> R1;
316 bits<4> R3;
317 bits<16> I2;
327 class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
329 field bits<48> Inst;
330 field bits<48> SoftFail = 0;
332 bits<4> R1;
333 bits<4> R3;
334 bits<16> RI2;
344 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
346 field bits<48> Inst;
347 field bits<48> SoftFail = 0;
349 bits<4> R1;
350 bits<4> R2;
351 bits<8> I3;
352 bits<8> I4;
353 bits<8> I5;
364 class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
366 field bits<48> Inst;
367 field bits<48> SoftFail = 0;
369 bits<4> R1;
370 bits<4> M3;
371 bits<16> I2;
381 class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
383 field bits<48> Inst;
384 field bits<48> SoftFail = 0;
386 bits<4> R1;
387 bits<32> I2;
395 class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
397 field bits<48> Inst;
398 field bits<48> SoftFail = 0;
400 bits<4> R1;
401 bits<32> RI2;
409 class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
411 field bits<48> Inst;
412 field bits<48> SoftFail = 0;
414 bits<4> M1;
415 bits<32> RI2;
423 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
425 field bits<48> Inst;
426 field bits<48> SoftFail = 0;
428 bits<4> R1;
429 bits<8> I2;
430 bits<4> M3;
431 bits<16> BD4;
441 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
443 field bits<16> Inst;
444 field bits<16> SoftFail = 0;
446 bits<4> R1;
447 bits<4> R2;
454 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
456 field bits<32> Inst;
457 field bits<32> SoftFail = 0;
459 bits<4> R1;
460 bits<4> R3;
461 bits<4> R2;
470 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
472 field bits<32> Inst;
473 field bits<32> SoftFail = 0;
475 bits<4> R1;
476 bits<4> R2;
484 class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
486 field bits<32> Inst;
487 field bits<32> SoftFail = 0;
489 bits<4> R1;
490 bits<4> R2;
491 bits<4> R3;
492 bits<4> M4;
501 class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
503 field bits<32> Inst;
504 field bits<32> SoftFail = 0;
506 bits<4> R1;
507 bits<4> R2;
508 bits<4> R3;
509 bits<4> M4;
518 class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
520 field bits<32> Inst;
521 field bits<32> SoftFail = 0;
523 bits<4> R1;
524 bits<4> R2;
525 bits<4> M3;
534 class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
536 field bits<32> Inst;
537 field bits<32> SoftFail = 0;
539 bits<4> R1;
540 bits<4> R2;
541 bits<4> M4;
550 class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
552 field bits<32> Inst;
553 field bits<32> SoftFail = 0;
555 bits<4> R1;
556 bits<4> R2;
557 bits<4> M3;
558 bits<4> M4;
567 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
569 field bits<48> Inst;
570 field bits<48> SoftFail = 0;
572 bits<4> R1;
573 bits<4> R2;
574 bits<4> M3;
575 bits<16> BD4;
586 class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
588 field bits<32> Inst;
589 field bits<32> SoftFail = 0;
591 bits<4> R1;
592 bits<20> XBD2;
601 class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
603 field bits<32> Inst;
604 field bits<32> SoftFail = 0;
606 bits<4> M1;
607 bits<20> XBD2;
616 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
618 field bits<48> Inst;
619 field bits<48> SoftFail = 0;
621 bits<4> R1;
622 bits<20> XBD2;
623 bits<4> M3;
635 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
637 field bits<48> Inst;
638 field bits<48> SoftFail = 0;
640 bits<4> R1;
641 bits<4> R3;
642 bits<20> XBD2;
654 class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
656 field bits<48> Inst;
657 field bits<48> SoftFail = 0;
659 bits<4> R1;
660 bits<28> XBD2;
671 class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
673 field bits<48> Inst;
674 field bits<48> SoftFail = 0;
676 bits<4> M1;
677 bits<28> XBD2;
688 class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
690 field bits<32> Inst;
691 field bits<32> SoftFail = 0;
693 bits<4> R1;
694 bits<4> R3;
695 bits<16> BD2;
703 class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
705 field bits<32> Inst;
706 field bits<32> SoftFail = 0;
708 bits<4> R1;
709 bits<4> M3;
710 bits<16> BD2;
718 class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
720 field bits<32> Inst;
721 field bits<32> SoftFail = 0;
723 bits<4> R1;
724 bits<4> R3;
725 bits<16> RI2;
733 class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
735 field bits<48> Inst;
736 field bits<48> SoftFail = 0;
738 bits<20> BDL1;
748 class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
750 field bits<48> Inst;
751 field bits<48> SoftFail = 0;
753 bits<4> R1;
754 bits<24> BDL2;
755 bits<4> M3;
764 class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
766 field bits<48> Inst;
767 field bits<48> SoftFail = 0;
769 bits<4> R1;
770 bits<4> R3;
771 bits<24> BD2;
782 class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
784 field bits<48> Inst;
785 field bits<48> SoftFail = 0;
787 bits<4> R1;
788 bits<4> M3;
789 bits<24> BD2;
800 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
802 field bits<32> Inst;
803 field bits<32> SoftFail = 0;
805 bits<16> BD1;
806 bits<8> I2;
813 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
815 field bits<48> Inst;
816 field bits<48> SoftFail = 0;
818 bits<16> BD1;
819 bits<16> I2;
826 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
828 field bits<48> Inst;
829 field bits<48> SoftFail = 0;
831 bits<24> BD1;
832 bits<8> I2;
842 class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
844 field bits<48> Inst;
845 field bits<48> SoftFail = 0;
847 bits<4> M1;
848 bits<16> RI2;
849 bits<16> BD3;
858 class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
860 field bits<48> Inst;
861 field bits<48> SoftFail = 0;
863 bits<24> BDL1;
864 bits<16> BD2;
871 class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
873 field bits<48> Inst;
874 field bits<48> SoftFail = 0;
876 bits<20> BDL1;
877 bits<20> BDL2;
886 class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
888 field bits<48> Inst;
889 field bits<48> SoftFail = 0;
891 bits<20> BDL1;
892 bits<16> BD2;
893 bits<4> I3;
902 class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
904 field bits<48> Inst;
905 field bits<48> SoftFail = 0;
907 bits<20> RBD1;
908 bits<16> BD2;
909 bits<4> R3;
918 class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
920 field bits<48> Inst;
921 field bits<48> SoftFail = 0;
923 bits<4> R1;
924 bits<16> BD2;
925 bits<4> R3;
926 bits<16> BD4;
935 class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
937 field bits<48> Inst;
938 field bits<48> SoftFail = 0;
940 bits<16> BD1;
941 bits<24> BDL2;
949 class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
951 field bits<48> Inst;
952 field bits<48> SoftFail = 0;
954 bits<16> BD1;
955 bits<16> BD2;
962 class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
964 field bits<48> Inst;
965 field bits<48> SoftFail = 0;
967 bits<16> BD1;
968 bits<16> BD2;
969 bits<4> R3;
978 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
980 field bits<32> Inst;
981 field bits<32> SoftFail = 0;
983 bits<16> BD2;
989 class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
991 field bits<48> Inst;
992 field bits<48> SoftFail = 0;
994 bits<5> V1;
995 bits<16> I2;
996 bits<4> M3;
1008 class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1010 field bits<48> Inst;
1011 field bits<48> SoftFail = 0;
1013 bits<5> V1;
1014 bits<8> I2;
1015 bits<8> I3;
1016 bits<4> M4;
1029 class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1031 field bits<48> Inst;
1032 field bits<48> SoftFail = 0;
1034 bits<5> V1;
1035 bits<5> V3;
1036 bits<16> I2;
1037 bits<4> M4;
1050 class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1052 field bits<48> Inst;
1053 field bits<48> SoftFail = 0;
1055 bits<5> V1;
1056 bits<5> V2;
1057 bits<5> V3;
1058 bits<8> I4;
1059 bits<4> M5;
1075 class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1077 field bits<48> Inst;
1078 field bits<48> SoftFail = 0;
1080 bits<5> V1;
1081 bits<5> V2;
1082 bits<12> I3;
1083 bits<4> M4;
1084 bits<4> M5;
1098 class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1100 field bits<48> Inst;
1101 field bits<48> SoftFail = 0;
1103 bits<5> V1;
1104 bits<5> V2;
1105 bits<5> V3;
1106 bits<8> I4;
1107 bits<4> M5;
1123 class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1125 field bits<48> Inst;
1126 field bits<48> SoftFail = 0;
1128 bits<5> V1;
1129 bits<5> V2;
1130 bits<8> I3;
1131 bits<8> I4;
1132 bits<4> M5;
1146 class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1148 field bits<48> Inst;
1149 field bits<48> SoftFail = 0;
1151 bits<5> V1;
1152 bits<16> I2;
1153 bits<4> I3;
1165 class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1167 field bits<48> Inst;
1168 field bits<48> SoftFail = 0;
1170 bits<5> V1;
1171 bits<4> R2;
1172 bits<8> I3;
1173 bits<4> M4;
1186 // Depending on the instruction mnemonic, certain bits may be or-ed into
1188 class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1189 bits<4> m4or = 0>
1191 field bits<48> Inst;
1192 field bits<48> SoftFail = 0;
1194 bits<5> V1;
1195 bits<5> V2;
1196 bits<4> M3;
1197 bits<4> M4;
1198 bits<4> M5;
1216 // Depending on the instruction mnemonic, certain bits may be or-ed into
1218 class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1219 bits<4> m5or = 0>
1221 field bits<48> Inst;
1222 field bits<48> SoftFail = 0;
1224 bits<5> V1;
1225 bits<5> V2;
1226 bits<5> V3;
1227 bits<4> M4;
1228 bits<4> M5;
1248 class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1250 field bits<48> Inst;
1251 field bits<48> SoftFail = 0;
1253 bits<5> V1;
1254 bits<5> V2;
1255 bits<5> V3;
1256 bits<4> M4;
1257 bits<4> M5;
1258 bits<4> M6;
1275 // Depending on the instruction mnemonic, certain bits may be or-ed into
1277 class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1278 bits<4> m6or = 0>
1280 field bits<48> Inst;
1281 field bits<48> SoftFail = 0;
1283 bits<5> V1;
1284 bits<5> V2;
1285 bits<5> V3;
1286 bits<5> V4;
1287 bits<4> M5;
1288 bits<4> M6;
1308 class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1310 field bits<48> Inst;
1311 field bits<48> SoftFail = 0;
1313 bits<5> V1;
1314 bits<5> V2;
1315 bits<5> V3;
1316 bits<5> V4;
1317 bits<4> M5;
1318 bits<4> M6;
1335 class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1337 field bits<48> Inst;
1338 field bits<48> SoftFail = 0;
1340 bits<5> V1;
1341 bits<4> R2;
1342 bits<4> R3;
1354 class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1356 field bits<48> Inst;
1357 field bits<48> SoftFail = 0;
1359 bits<5> V1;
1371 class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1373 field bits<48> Inst;
1374 field bits<48> SoftFail = 0;
1376 bits<5> V1;
1377 bits<5> V2;
1378 bits<4> M3;
1394 class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1396 field bits<48> Inst;
1397 field bits<48> SoftFail = 0;
1399 bits<4> R1;
1400 bits<5> V2;
1401 bits<4> M3;
1415 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1417 field bits<48> Inst;
1418 field bits<48> SoftFail = 0;
1420 bits<5> V1;
1421 bits<16> BD2;
1422 bits<5> V3;
1423 bits<4> M4;
1436 class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1438 field bits<48> Inst;
1439 field bits<48> SoftFail = 0;
1441 bits<5> V1;
1442 bits<16> BD2;
1443 bits<4> R3;
1444 bits<4> M4;
1456 class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1458 field bits<48> Inst;
1459 field bits<48> SoftFail = 0;
1461 bits<4> R1;
1462 bits<16> BD2;
1463 bits<5> V3;
1464 bits<4> M4;
1477 class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1479 field bits<48> Inst;
1480 field bits<48> SoftFail = 0;
1482 bits<5> V1;
1483 bits<16> BD2;
1484 bits<4> R3;
1496 class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1498 field bits<48> Inst;
1499 field bits<48> SoftFail = 0;
1501 bits<5> V1;
1502 bits<21> VBD2;
1503 bits<4> M3;
1515 class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1517 field bits<48> Inst;
1518 field bits<48> SoftFail = 0;
1520 bits<5> V1;
1521 bits<20> XBD2;
1522 bits<4> M3;
1533 class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1535 field bits<48> Inst;
1536 field bits<48> SoftFail = 0;
1538 bits<5> V1;
1539 bits<16> BD2;
1540 bits<8> I3;
1557 bits<16> enc;
1564 bits<32> enc;
1572 bits<48> enc;
1580 bits<48> enc;
1589 bits<48> enc;
1597 bits<16> enc;
1604 bits<32> enc;
1611 bits<32> enc;
1618 bits<48> enc;
1626 bits<32> enc;
1634 bits <48> enc;
1644 bits<32> enc;
1651 bits<48> enc;
1659 bits<32> enc;
1666 bits<48> enc;
1676 bits<48> enc;
1684 bits<48> enc;
1692 bits<32> enc;
1699 bits<32> enc;
1706 bits<48> enc;
1714 bits<48> enc;
1721 bits<48> enc;
1728 bits<48> enc;
1735 bits<48> enc;
1773 class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
1775 bits<4> ccmask = ccmaskin;
1788 // Condition masks for general instructions that can set all 4 bits.
1972 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1980 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
1984 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1990 class StoreInherentS<string mnemonic, bits<16> opcode,
1991 SDPatternOperator operator, bits<5> bytes>
1998 class SideEffectInherentE<string mnemonic, bits<16>opcode>
2001 class SideEffectInherentS<string mnemonic, bits<16> opcode,
2007 class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
2014 class CallRI<string mnemonic, bits<12> opcode>
2019 class CallRIL<string mnemonic, bits<12> opcode>
2023 class CallRR<string mnemonic, bits<8> opcode>
2027 class CallRX<string mnemonic, bits<8> opcode>
2031 class CondBranchRI<string mnemonic, bits<12> opcode,
2039 class AsmCondBranchRI<string mnemonic, bits<12> opcode>
2043 class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
2051 class CondBranchRIL<string mnemonic, bits<12> opcode>
2057 class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
2061 class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
2068 class CondBranchRR<string mnemonic, bits<8> opcode>
2074 class AsmCondBranchRR<string mnemonic, bits<8> opcode>
2078 class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
2086 class CondBranchRX<string mnemonic, bits<8> opcode>
2092 class AsmCondBranchRX<string mnemonic, bits<8> opcode>
2096 class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
2103 class CondBranchRXY<string mnemonic, bits<16> opcode>
2110 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
2116 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
2126 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
2131 class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
2136 class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
2144 multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
2151 class CmpBranchRIEb<string mnemonic, bits<16> opcode,
2157 class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
2163 class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
2171 multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
2178 class CmpBranchRIEc<string mnemonic, bits<16> opcode,
2184 class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
2190 class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
2198 multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
2205 class CmpBranchRRFc<string mnemonic, bits<16> opcode,
2210 class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
2215 multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
2222 class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
2230 class CmpBranchRRS<string mnemonic, bits<16> opcode,
2236 class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
2242 class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
2250 multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
2257 class CmpBranchRIS<string mnemonic, bits<16> opcode,
2263 class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
2269 class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
2277 multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
2284 class CmpBranchRSYb<string mnemonic, bits<16> opcode,
2289 class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
2294 multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
2301 class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
2309 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2316 class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2323 class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2330 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2337 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2344 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2351 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2358 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2366 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2374 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2382 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2389 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2396 multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2397 bits<16> rsyOpcode, RegisterOperand cls> {
2406 class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2413 class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
2420 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2432 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2433 RegisterOperand cls, bits<5> bytes,
2444 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2445 RegisterOperand cls, bits<5> bytes,
2456 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2458 bits<5> bytes> {
2468 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2469 TypedReg tr, bits<5> bytes, bits<4> type = 0>
2478 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2479 SDPatternOperator operator, bits<5> bytes>
2488 class StoreLengthVRSd<string mnemonic, bits<16> opcode,
2489 SDPatternOperator operator, bits<5> bytes>
2497 class StoreLengthVSI<string mnemonic, bits<16> opcode,
2498 SDPatternOperator operator, bits<5> bytes>
2506 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2513 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2520 multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2521 bits<16> rsyOpcode, RegisterOperand cls> {
2530 class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
2543 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2551 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2559 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2567 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2577 class StoreSSE<string mnemonic, bits<16> opcode>
2583 class CondStoreRSY<string mnemonic, bits<16> opcode,
2584 RegisterOperand cls, bits<5> bytes,
2595 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
2596 RegisterOperand cls, bits<5> bytes,
2605 class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
2606 RegisterOperand cls, bits<5> bytes,
2616 multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
2617 RegisterOperand cls, bits<5> bytes,
2624 class SideEffectUnaryI<string mnemonic, bits<8> opcode, Immediate imm>
2628 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2634 class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2641 class SideEffectUnaryS<string mnemonic, bits<16> opcode,
2642 SDPatternOperator operator, bits<5> bytes,
2650 class SideEffectAddressS<string mnemonic, bits<16> opcode,
2656 class LoadAddressRX<string mnemonic, bits<8> opcode,
2662 class LoadAddressRXY<string mnemonic, bits<16> opcode,
2668 multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
2669 bits<16> rxyOpcode, SDPatternOperator operator> {
2678 class LoadAddressRIL<string mnemonic, bits<12> opcode,
2684 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2693 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2702 class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2710 class UnaryMemRRFc<string mnemonic, bits<16> opcode,
2719 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2725 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2731 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2743 class CondUnaryRSY<string mnemonic, bits<16> opcode,
2745 bits<5> bytes, AddressingMode mode = bdaddr20only>
2761 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
2762 RegisterOperand cls, bits<5> bytes,
2773 class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
2774 RegisterOperand cls, bits<5> bytes,
2786 multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
2788 RegisterOperand cls, bits<5> bytes,
2795 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2796 RegisterOperand cls, bits<5> bytes,
2807 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2808 RegisterOperand cls, bits<5> bytes>
2819 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2820 RegisterOperand cls, bits<5> bytes,
2831 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2833 bits<5> bytes> {
2843 class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2844 TypedReg tr, Immediate imm, bits<4> type = 0>
2851 class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, Immediate imm>
2855 class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2856 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
2857 bits<4> m5 = 0>
2866 class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
2867 bits<4> m5 = 0>
2874 class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
2885 multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
2888 TypedReg tr1, TypedReg tr2, bits<4> type> {
2902 multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
2912 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2913 TypedReg tr, bits<5> bytes, bits<4> type = 0>
2922 class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
2928 class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
2933 class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
2938 class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
2948 class SideEffectBinaryRRE<string mnemonic, bits<16> opcode,
2953 class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode,
2961 class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode,
2968 class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
2973 class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
2977 class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
2982 class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
2986 class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
2991 class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
2995 class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
2999 class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
3007 class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
3015 class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
3023 class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
3032 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3043 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3054 class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3063 class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3072 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3084 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
3096 class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3105 class BinaryMemRRFc<string mnemonic, bits<16> opcode,
3113 multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
3119 class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3124 class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3131 class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3145 class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3155 class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
3165 multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
3172 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3181 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3187 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
3199 class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3213 class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3223 class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
3233 multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
3240 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3249 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3259 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3265 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3276 class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3283 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3284 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3297 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3298 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3312 class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3314 SDPatternOperator load, bits<5> bytes>
3324 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3325 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3338 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3340 SDPatternOperator load, bits<5> bytes> {
3351 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3360 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3369 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
3370 bits<16> siyOpcode, SDPatternOperator operator,
3380 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3386 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3387 TypedReg tr, bits<4> type>
3394 class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
3399 class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3400 TypedReg tr1, TypedReg tr2, bits<4> type>
3408 class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
3413 class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3414 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
3423 class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
3428 class BinaryVRIh<string mnemonic, bits<16> opcode>
3433 class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3434 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
3443 class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3448 class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3449 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
3450 bits<4> modifier = 0>
3461 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
3464 TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
3472 class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
3483 multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
3486 TypedReg tr1, TypedReg tr2, bits<4> type> {
3500 multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3510 class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3511 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
3512 bits<4> m6 = 0>
3522 class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
3523 bits<4> m6 = 0>
3531 class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
3540 multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
3543 TypedReg tr2, bits<4> type, bits<4> m5,
3544 bits<4> modifier = 0> {
3552 class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
3558 class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3564 class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
3568 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3569 TypedReg tr1, TypedReg tr2, bits<4> type>
3577 class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
3582 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3583 bits<5> bytes>
3592 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3593 TypedReg tr, bits<4> type>
3600 class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
3605 class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3606 bits<5> bytes>
3614 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3615 TypedReg tr, bits<5> bytes>
3624 class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3625 bits<5> bytes, AddressingMode mode = bdaddr12only>
3632 class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3633 bits<5> bytes, AddressingMode mode = bdaddr20only>
3640 multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
3641 bits<16> rsyOpcode, RegisterOperand cls,
3642 bits<5> bytes> {
3652 class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3659 class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3660 bits<5> bytes>
3668 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3676 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
3677 SDPatternOperator operator, TypedReg tr, bits<5> bytes,
3686 class MemoryBinarySSd<string mnemonic, bits<8> opcode,
3692 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3702 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3712 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3720 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3728 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3741 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3742 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3754 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3755 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3767 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3768 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3780 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3782 SDPatternOperator load, bits<5> bytes> {
3793 class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3794 bits<5> bytes, AddressingMode mode = bdaddr12only>
3801 class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3802 bits<5> bytes, AddressingMode mode = bdaddr20only>
3809 multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3810 RegisterOperand cls, bits<5> bytes> {
3819 class CompareSSb<string mnemonic, bits<8> opcode>
3827 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3837 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3846 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3856 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
3868 class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3869 TypedReg tr, bits<4> type>
3879 class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
3887 class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3895 class CompareVRRh<string mnemonic, bits<16> opcode>
3901 class TestInherentS<string mnemonic, bits<16> opcode,
3907 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3915 class TestBinarySIL<string mnemonic, bits<16> opcode,
3921 class TestRSL<string mnemonic, bits<16> opcode>
3927 class TestVRRg<string mnemonic, bits<16> opcode>
3931 class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
3936 class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
3944 class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode,
3952 class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
3964 class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
3970 multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode,
3977 class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
3987 multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
3994 class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
4000 class TernaryRRFa<string mnemonic, bits<16> opcode,
4006 class TernaryRRFb<string mnemonic, bits<16> opcode,
4016 class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4022 class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4033 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4034 bits<5> bytes, AddressingMode mode = bdaddr12only>
4045 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4046 bits<5> bytes, AddressingMode mode = bdaddr20only>
4057 multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4058 RegisterOperand cls, bits<5> bytes> {
4067 class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
4073 class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
4079 class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
4088 class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
4097 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4099 SDPatternOperator load, bits<5> bytes>
4113 class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4123 class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4124 TypedReg tr1, TypedReg tr2, bits<4> type>
4134 class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4139 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4140 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
4151 class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4156 class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4157 TypedReg tr1, TypedReg tr2, bits<4> type,
4158 SDPatternOperator m5mask, bits<4> m5or>
4172 multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
4175 TypedReg tr1, TypedReg tr2, bits<4> type,
4176 bits<4> modifier = 0> {
4190 multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
4200 class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4212 class TernaryVRRcFloat<string mnemonic, bits<16> opcode,
4214 bits<4> type = 0, bits<4> m5 = 0>
4225 class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode>
4231 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4232 TypedReg tr1, TypedReg tr2, bits<4> type = 0>
4243 class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
4250 class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4251 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
4262 class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
4267 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4268 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
4280 class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
4288 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
4299 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4300 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
4313 class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4314 TypedReg tr1, TypedReg tr2, bits<4> type>
4327 class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
4336 class QuaternaryVRIf<string mnemonic, bits<16> opcode>
4342 class QuaternaryVRIg<string mnemonic, bits<16> opcode>
4348 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
4350 TypedReg tr3, TypedReg tr4, bits<4> type,
4351 SDPatternOperator m6mask = imm32zx4, bits<4> m6or = 0>
4363 class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode>
4371 multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
4374 TypedReg tr1, TypedReg tr2, bits<4> type,
4375 bits<4> modifier = 0> {
4391 multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
4399 class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode,
4405 multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode,
4414 class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode,
4420 multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
4428 class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
4434 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4443 class CmpSwapRRE<string mnemonic, bits<16> opcode,
4453 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4464 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4475 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4485 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4495 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
4500 class PrefetchRILPC<string mnemonic, bits<12> opcode,
4511 class BranchPreloadSMI<string mnemonic, bits<8> opcode>
4516 class BranchPreloadMII<string mnemonic, bits<8> opcode>
4526 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
4557 RegisterOperand cls, bits<5> bytes,
4615 SDPatternOperator load, bits<5> bytes,
4657 bits<5> bytes, AddressingMode mode = bdaddr20only>
4672 class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
4682 bits<5> bytes, AddressingMode mode = bdxaddr20only>
4784 multiclass MemorySS<string mnemonic, bits<8> opcode,
4800 multiclass CompareMemorySS<string mnemonic, bits<8> opcode,
4820 multiclass StringRRE<string mnemonic, bits<16> opcode,