Lines Matching refs:Base

294   uint64_t Base = Field >> 12;  in decodeBDAddr12Operand()  local
296 assert(Base < 16 && "Invalid BDAddr12"); in decodeBDAddr12Operand()
297 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
304 uint64_t Base = Field >> 20; in decodeBDAddr20Operand() local
306 assert(Base < 16 && "Invalid BDAddr20"); in decodeBDAddr20Operand()
307 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
315 uint64_t Base = (Field >> 12) & 0xf; in decodeBDXAddr12Operand() local
318 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
327 uint64_t Base = (Field >> 20) & 0xf; in decodeBDXAddr20Operand() local
330 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
339 uint64_t Base = (Field >> 12) & 0xf; in decodeBDLAddr12Len4Operand() local
342 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len4Operand()
351 uint64_t Base = (Field >> 12) & 0xf; in decodeBDLAddr12Len8Operand() local
354 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
363 uint64_t Base = (Field >> 12) & 0xf; in decodeBDRAddr12Operand() local
366 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDRAddr12Operand()
375 uint64_t Base = (Field >> 12) & 0xf; in decodeBDVAddr12Operand() local
378 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDVAddr12Operand()