42 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,  in RISCVTargetLowering()  function in RISCVTargetLowering
172 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,  in getSetCCResultType()
179 bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
207 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
233 bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const {  in isLegalICmpImmediate()
237 bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {  in isLegalAddImmediate()
244 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {  in isTruncateFree()
252 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {  in isTruncateFree()
261 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
275 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {  in isSExtCheaperThanZExt()
318 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
340 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,  in lowerGlobalAddress()
366 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,  in lowerBlockAddress()
385 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,  in lowerConstantPool()
408 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in lowerSELECT()
448 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {  in lowerVASTART()
463 SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,  in lowerFRAMEADDR()
486 SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,  in lowerRETURNADDR()
542 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
659 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,  in EmitInstrWithCustomInserter()
927 void RISCVTargetLowering::analyzeInputArgs(  in analyzeInputArgs()
952 void RISCVTargetLowering::analyzeOutputArgs(  in analyzeOutputArgs()
1090 SDValue RISCVTargetLowering::LowerFormalArguments(  in LowerFormalArguments()
1233 bool RISCVTargetLowering::IsEligibleForTailCallOptimization(  in IsEligibleForTailCallOptimization()
1314 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
1562 bool RISCVTargetLowering::CanLowerReturn(  in CanLowerReturn()
1578 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,  in LowerReturn()
1660 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
1687 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,  in getRegForInlineAsmConstraint()
1704 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,  in emitLeadingFence()
1714 Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder,  in emitTrailingFence()
1723 RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {  in shouldExpandAtomicRMWInIR()
1754 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(  in emitMaskedAtomicRMWIntrinsic()
1783 RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(  in shouldExpandAtomicCmpXchgInIR()
1791 Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(  in emitMaskedAtomicCmpXchgIntrinsic()