Lines Matching refs:ArgValue
1132 SDValue ArgValue; in LowerFormalArguments() local
1136 ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL); in LowerFormalArguments()
1138 ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL); in LowerFormalArguments()
1140 ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL); in LowerFormalArguments()
1146 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, in LowerFormalArguments()
1153 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue, in LowerFormalArguments()
1161 InVals.push_back(ArgValue); in LowerFormalArguments()
1207 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); in LowerFormalArguments() local
1210 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, in LowerFormalArguments()
1382 SDValue ArgValue = OutVals[i]; in LowerCall() local
1390 RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue); in LowerCall()
1423 DAG.getStore(Chain, DL, ArgValue, SpillSlot, in LowerCall()
1439 ArgValue = SpillSlot; in LowerCall()
1441 ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL); in LowerCall()
1446 ArgValue = ByValArgs[j++]; in LowerCall()
1450 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
1465 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo())); in LowerCall()