Lines Matching refs:PPC
102 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
104 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
114 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
115 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
133 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
137 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
138 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
194 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
195 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
197 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
198 PPC::CRBITRCRegClass.contains(Reg); in getOperandLatency()
210 case PPC::DIR_7400: in getOperandLatency()
211 case PPC::DIR_750: in getOperandLatency()
212 case PPC::DIR_970: in getOperandLatency()
213 case PPC::DIR_E5500: in getOperandLatency()
214 case PPC::DIR_PWR4: in getOperandLatency()
215 case PPC::DIR_PWR5: in getOperandLatency()
216 case PPC::DIR_PWR5X: in getOperandLatency()
217 case PPC::DIR_PWR6: in getOperandLatency()
218 case PPC::DIR_PWR6X: in getOperandLatency()
219 case PPC::DIR_PWR7: in getOperandLatency()
220 case PPC::DIR_PWR8: in getOperandLatency()
238 case PPC::FADD: in isAssociativeAndCommutative()
239 case PPC::FADDS: in isAssociativeAndCommutative()
241 case PPC::FMUL: in isAssociativeAndCommutative()
242 case PPC::FMULS: in isAssociativeAndCommutative()
244 case PPC::VADDFP: in isAssociativeAndCommutative()
246 case PPC::XSADDDP: in isAssociativeAndCommutative()
247 case PPC::XVADDDP: in isAssociativeAndCommutative()
248 case PPC::XVADDSP: in isAssociativeAndCommutative()
249 case PPC::XSADDSP: in isAssociativeAndCommutative()
251 case PPC::XSMULDP: in isAssociativeAndCommutative()
252 case PPC::XVMULDP: in isAssociativeAndCommutative()
253 case PPC::XVMULSP: in isAssociativeAndCommutative()
254 case PPC::XSMULSP: in isAssociativeAndCommutative()
256 case PPC::QVFADD: in isAssociativeAndCommutative()
257 case PPC::QVFADDS: in isAssociativeAndCommutative()
258 case PPC::QVFADDSs: in isAssociativeAndCommutative()
260 case PPC::QVFMUL: in isAssociativeAndCommutative()
261 case PPC::QVFMULS: in isAssociativeAndCommutative()
262 case PPC::QVFMULSs: in isAssociativeAndCommutative()
290 case PPC::EXTSW: in isCoalescableExtInstr()
291 case PPC::EXTSW_32: in isCoalescableExtInstr()
292 case PPC::EXTSW_32_64: in isCoalescableExtInstr()
295 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
328 case PPC::LI: in isReallyTriviallyReMaterializable()
329 case PPC::LI8: in isReallyTriviallyReMaterializable()
330 case PPC::LIS: in isReallyTriviallyReMaterializable()
331 case PPC::LIS8: in isReallyTriviallyReMaterializable()
332 case PPC::QVGPCI: in isReallyTriviallyReMaterializable()
333 case PPC::ADDIStocHA: in isReallyTriviallyReMaterializable()
334 case PPC::ADDItocL: in isReallyTriviallyReMaterializable()
335 case PPC::LOAD_STACK_GUARD: in isReallyTriviallyReMaterializable()
363 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo) in commuteInstructionImpl()
447 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); in findCommutedOpIndices()
463 default: Opcode = PPC::NOP; break; in insertNoop()
464 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; in insertNoop()
465 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
466 …case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling mod… in insertNoop()
468 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
477 NopInst.setOpcode(PPC::NOP); in getNoop()
501 if (I->getOpcode() == PPC::B && in analyzeBranch()
517 if (LastInst.getOpcode() == PPC::B) { in analyzeBranch()
522 } else if (LastInst.getOpcode() == PPC::BCC) { in analyzeBranch()
530 } else if (LastInst.getOpcode() == PPC::BC) { in analyzeBranch()
535 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
538 } else if (LastInst.getOpcode() == PPC::BCn) { in analyzeBranch()
543 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
546 } else if (LastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
547 LastInst.getOpcode() == PPC::BDNZ) { in analyzeBranch()
554 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
557 } else if (LastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
558 LastInst.getOpcode() == PPC::BDZ) { in analyzeBranch()
565 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
582 if (SecondLastInst.getOpcode() == PPC::BCC && in analyzeBranch()
583 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
592 } else if (SecondLastInst.getOpcode() == PPC::BC && in analyzeBranch()
593 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
598 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
602 } else if (SecondLastInst.getOpcode() == PPC::BCn && in analyzeBranch()
603 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
608 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
612 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
613 SecondLastInst.getOpcode() == PPC::BDNZ) && in analyzeBranch()
614 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
622 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
626 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
627 SecondLastInst.getOpcode() == PPC::BDZ) && in analyzeBranch()
628 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
636 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
644 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) { in analyzeBranch()
666 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && in removeBranch()
667 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
668 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
669 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
679 if (I->getOpcode() != PPC::BCC && in removeBranch()
680 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
681 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
682 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
707 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in insertBranch()
708 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
710 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
711 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
712 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
713 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
714 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
715 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
717 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
725 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
727 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
728 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
729 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
730 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
731 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
732 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
734 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
738 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); in insertBranch()
752 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in canInsertSelect()
763 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
764 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
765 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
766 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
794 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
795 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
797 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
798 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
801 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL; in insertSelect()
802 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm()); in insertSelect()
807 case PPC::PRED_EQ: in insertSelect()
808 case PPC::PRED_EQ_MINUS: in insertSelect()
809 case PPC::PRED_EQ_PLUS: in insertSelect()
810 SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
811 case PPC::PRED_NE: in insertSelect()
812 case PPC::PRED_NE_MINUS: in insertSelect()
813 case PPC::PRED_NE_PLUS: in insertSelect()
814 SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
815 case PPC::PRED_LT: in insertSelect()
816 case PPC::PRED_LT_MINUS: in insertSelect()
817 case PPC::PRED_LT_PLUS: in insertSelect()
818 SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
819 case PPC::PRED_GE: in insertSelect()
820 case PPC::PRED_GE_MINUS: in insertSelect()
821 case PPC::PRED_GE_PLUS: in insertSelect()
822 SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
823 case PPC::PRED_GT: in insertSelect()
824 case PPC::PRED_GT_MINUS: in insertSelect()
825 case PPC::PRED_GT_PLUS: in insertSelect()
826 SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
827 case PPC::PRED_LE: in insertSelect()
828 case PPC::PRED_LE_MINUS: in insertSelect()
829 case PPC::PRED_LE_PLUS: in insertSelect()
830 SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
831 case PPC::PRED_UN: in insertSelect()
832 case PPC::PRED_UN_MINUS: in insertSelect()
833 case PPC::PRED_UN_PLUS: in insertSelect()
834 SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
835 case PPC::PRED_NU: in insertSelect()
836 case PPC::PRED_NU_MINUS: in insertSelect()
837 case PPC::PRED_NU_PLUS: in insertSelect()
838 SubIdx = PPC::sub_un; SwapOps = true; break; in insertSelect()
839 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break; in insertSelect()
840 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break; in insertSelect()
849 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
850 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
852 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
853 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; in insertSelect()
867 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT || in getCRBitValue()
868 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT || in getCRBitValue()
869 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT || in getCRBitValue()
870 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT) in getCRBitValue()
872 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT || in getCRBitValue()
873 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT || in getCRBitValue()
874 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT || in getCRBitValue()
875 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT) in getCRBitValue()
877 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ || in getCRBitValue()
878 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ || in getCRBitValue()
879 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ || in getCRBitValue()
880 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ) in getCRBitValue()
882 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN || in getCRBitValue()
883 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN || in getCRBitValue()
884 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN || in getCRBitValue()
885 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN) in getCRBitValue()
899 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
900 PPC::VSRCRegClass.contains(SrcReg)) { in copyPhysReg()
902 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
908 } else if (PPC::F8RCRegClass.contains(SrcReg) && in copyPhysReg()
909 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
911 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
920 if (PPC::CRBITRCRegClass.contains(SrcReg) && in copyPhysReg()
921 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
923 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg()
927 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) in copyPhysReg()
933 } else if (PPC::CRRCRegClass.contains(SrcReg) && in copyPhysReg()
934 PPC::G8RCRegClass.contains(DestReg)) { in copyPhysReg()
935 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg); in copyPhysReg()
938 } else if (PPC::CRRCRegClass.contains(SrcReg) && in copyPhysReg()
939 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
940 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg); in copyPhysReg()
943 } else if (PPC::G8RCRegClass.contains(SrcReg) && in copyPhysReg()
944 PPC::VSFRCRegClass.contains(DestReg)) { in copyPhysReg()
945 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
949 } else if (PPC::VSFRCRegClass.contains(SrcReg) && in copyPhysReg()
950 PPC::G8RCRegClass.contains(DestReg)) { in copyPhysReg()
951 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
954 } else if (PPC::SPERCRegClass.contains(SrcReg) && in copyPhysReg()
955 PPC::SPE4RCRegClass.contains(DestReg)) { in copyPhysReg()
956 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg); in copyPhysReg()
959 } else if (PPC::SPE4RCRegClass.contains(SrcReg) && in copyPhysReg()
960 PPC::SPERCRegClass.contains(DestReg)) { in copyPhysReg()
961 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg); in copyPhysReg()
968 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
969 Opc = PPC::OR; in copyPhysReg()
970 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
971 Opc = PPC::OR8; in copyPhysReg()
972 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
973 Opc = PPC::FMR; in copyPhysReg()
974 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
975 Opc = PPC::MCRF; in copyPhysReg()
976 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
977 Opc = PPC::VOR; in copyPhysReg()
978 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
987 Opc = PPC::XXLOR; in copyPhysReg()
988 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) || in copyPhysReg()
989 PPC::VSSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
990 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf; in copyPhysReg()
991 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
992 Opc = PPC::QVFMR; in copyPhysReg()
993 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
994 Opc = PPC::QVFMRs; in copyPhysReg()
995 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
996 Opc = PPC::QVFMRb; in copyPhysReg()
997 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
998 Opc = PPC::CROR; in copyPhysReg()
999 else if (PPC::SPERCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1000 Opc = PPC::EVOR; in copyPhysReg()
1019 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getStoreOpcodeForSpill()
1020 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1022 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in getStoreOpcodeForSpill()
1023 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1025 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1027 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1029 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1031 } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1033 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1035 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1037 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1039 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1041 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1043 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1045 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1047 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1049 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1051 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1053 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
1059 if (PPC::GPRCRegClass.contains(Reg) || in getStoreOpcodeForSpill()
1060 PPC::GPRC_NOR0RegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1062 } else if (PPC::G8RCRegClass.contains(Reg) || in getStoreOpcodeForSpill()
1063 PPC::G8RC_NOX0RegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1065 } else if (PPC::F8RCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1067 } else if (PPC::F4RCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1069 } else if (PPC::CRRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1071 } else if (PPC::CRBITRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1073 } else if (PPC::VRRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1075 } else if (PPC::VSRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1077 } else if (PPC::VSFRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1079 } else if (PPC::VSSRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1081 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1083 } else if (PPC::QFRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1085 } else if (PPC::QSRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1087 } else if (PPC::QBRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1089 } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) { in getStoreOpcodeForSpill()
1105 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getLoadOpcodeForSpill()
1106 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1108 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in getLoadOpcodeForSpill()
1109 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1111 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1113 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1115 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1117 } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1119 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1121 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1123 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1125 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1127 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1129 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1131 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1133 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1135 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1137 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1139 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) { in getLoadOpcodeForSpill()
1145 if (PPC::GPRCRegClass.contains(Reg) || in getLoadOpcodeForSpill()
1146 PPC::GPRC_NOR0RegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1148 } else if (PPC::G8RCRegClass.contains(Reg) || in getLoadOpcodeForSpill()
1149 PPC::G8RC_NOX0RegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1151 } else if (PPC::F8RCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1153 } else if (PPC::F4RCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1155 } else if (PPC::CRRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1157 } else if (PPC::CRBITRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1159 } else if (PPC::VRRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1161 } else if (PPC::VSRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1163 } else if (PPC::VSFRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1165 } else if (PPC::VSSRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1167 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1169 } else if (PPC::QFRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1171 } else if (PPC::QSRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1173 } else if (PPC::QBRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1175 } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) { in getLoadOpcodeForSpill()
1188 unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC); in StoreRegToStackSlot()
1198 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
1199 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
1202 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
1245 unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC); in LoadRegFromStackSlot()
1250 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in LoadRegFromStackSlot()
1251 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in LoadRegFromStackSlot()
1254 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) in LoadRegFromStackSlot()
1282 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) in loadRegFromStackSlot()
1283 RC = &PPC::VSRCRegClass; in loadRegFromStackSlot()
1301 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) in reverseBranchCondition()
1305 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in reverseBranchCondition()
1314 if (DefOpc != PPC::LI && DefOpc != PPC::LI8) in FoldImmediate()
1348 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && in FoldImmediate()
1349 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) in FoldImmediate()
1362 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in FoldImmediate()
1364 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in FoldImmediate()
1365 PPC::ZERO8 : PPC::ZERO; in FoldImmediate()
1380 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8)) in MBBDefinesCTR()
1425 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
1426 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
1428 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
1429 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); in PredicateInstruction()
1430 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
1431 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
1433 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
1434 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
1437 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
1444 } else if (OpC == PPC::B) { in PredicateInstruction()
1445 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
1447 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
1448 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); in PredicateInstruction()
1449 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
1453 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
1457 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
1461 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
1469 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
1477 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL || in PredicateInstruction()
1478 OpC == PPC::BCTRL8) { in PredicateInstruction()
1479 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) in PredicateInstruction()
1482 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8; in PredicateInstruction()
1485 if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
1486 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
1487 : (setLR ? PPC::BCCTRL : PPC::BCCTR))); in PredicateInstruction()
1490 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
1491 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
1492 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); in PredicateInstruction()
1497 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) in PredicateInstruction()
1498 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); in PredicateInstruction()
1513 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) in SubsumesPredicate()
1515 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) in SubsumesPredicate()
1522 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); in SubsumesPredicate()
1523 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); in SubsumesPredicate()
1529 if (P1 == PPC::PRED_LE && in SubsumesPredicate()
1530 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
1532 if (P1 == PPC::PRED_GE && in SubsumesPredicate()
1533 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
1548 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, in DefinesPredicate()
1549 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; in DefinesPredicate()
1580 case PPC::B: in isPredicable()
1581 case PPC::BLR: in isPredicable()
1582 case PPC::BLR8: in isPredicable()
1583 case PPC::BCTR: in isPredicable()
1584 case PPC::BCTR8: in isPredicable()
1585 case PPC::BCTRL: in isPredicable()
1586 case PPC::BCTRL8: in isPredicable()
1598 case PPC::CMPWI: in analyzeCompare()
1599 case PPC::CMPLWI: in analyzeCompare()
1600 case PPC::CMPDI: in analyzeCompare()
1601 case PPC::CMPLDI: in analyzeCompare()
1607 case PPC::CMPW: in analyzeCompare()
1608 case PPC::CMPLW: in analyzeCompare()
1609 case PPC::CMPD: in analyzeCompare()
1610 case PPC::CMPLD: in analyzeCompare()
1611 case PPC::FCMPUS: in analyzeCompare()
1612 case PPC::FCMPUD: in analyzeCompare()
1632 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD) in optimizeCompareInstr()
1644 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW; in optimizeCompareInstr()
1645 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW; in optimizeCompareInstr()
1646 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD; in optimizeCompareInstr()
1681 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
1682 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
1683 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
1685 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE) in optimizeCompareInstr()
1687 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
1688 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
1690 if (SubIdx != PPC::sub_eq) in optimizeCompareInstr()
1715 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate; in optimizeCompareInstr()
1744 if (UseMI->getOpcode() != PPC::BCC) in optimizeCompareInstr()
1747 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
1748 PPC::Predicate NewPred = Pred; in optimizeCompareInstr()
1749 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
1750 unsigned PredHint = PPC::getPredicateHint(Pred); in optimizeCompareInstr()
1755 if (Immed == -1 && PredCond == PPC::PRED_GT) in optimizeCompareInstr()
1758 NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint); in optimizeCompareInstr()
1759 else if (Immed == -1 && PredCond == PPC::PRED_LE) in optimizeCompareInstr()
1761 NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint); in optimizeCompareInstr()
1762 else if (Immed == 1 && PredCond == PPC::PRED_LT) in optimizeCompareInstr()
1764 NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint); in optimizeCompareInstr()
1765 else if (Immed == 1 && PredCond == PPC::PRED_GE) in optimizeCompareInstr()
1767 NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint); in optimizeCompareInstr()
1786 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || in optimizeCompareInstr()
1787 Instr.readsRegister(PPC::CR0, TRI))) in optimizeCompareInstr()
1796 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW || in optimizeCompareInstr()
1797 OpC == PPC::CMPD || OpC == PPC::CMPLD) && in optimizeCompareInstr()
1798 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) && in optimizeCompareInstr()
1821 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 || in optimizeCompareInstr()
1822 MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8) in optimizeCompareInstr()
1825 NewOpC = PPC::getRecordFormOpcode(MIOpC); in optimizeCompareInstr()
1826 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1) in optimizeCompareInstr()
1860 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
1861 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
1862 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
1864 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && in optimizeCompareInstr()
1868 PPC::getSwappedPredicate(Pred))); in optimizeCompareInstr()
1869 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
1870 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
1872 assert((!equalityOnly || NewSubReg == PPC::sub_eq) && in optimizeCompareInstr()
1875 if (NewSubReg == PPC::sub_lt) in optimizeCompareInstr()
1876 NewSubReg = PPC::sub_gt; in optimizeCompareInstr()
1877 else if (NewSubReg == PPC::sub_gt) in optimizeCompareInstr()
1878 NewSubReg = PPC::sub_lt; in optimizeCompareInstr()
1897 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); in optimizeCompareInstr()
1901 MI->clearRegisterDeads(PPC::CR0); in optimizeCompareInstr()
1913 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) { in optimizeCompareInstr()
1928 NewOpC = MIOpC == PPC::RLWINM ? in optimizeCompareInstr()
1929 (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) : in optimizeCompareInstr()
1930 (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8); in optimizeCompareInstr()
1938 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8; in optimizeCompareInstr()
1947 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) { in optimizeCompareInstr()
1951 NewOpC = PPC::ANDIo8; in optimizeCompareInstr()
1974 assert(MI->definesRegister(PPC::CR0) && in optimizeCompareInstr()
1995 if (Opcode == PPC::INLINEASM) { in getInstSizeInBytes()
2051 case PPC::DFLOADf32: in expandVSXMemPseudo()
2052 UpperOpcode = PPC::LXSSP; in expandVSXMemPseudo()
2053 LowerOpcode = PPC::LFS; in expandVSXMemPseudo()
2055 case PPC::DFLOADf64: in expandVSXMemPseudo()
2056 UpperOpcode = PPC::LXSD; in expandVSXMemPseudo()
2057 LowerOpcode = PPC::LFD; in expandVSXMemPseudo()
2059 case PPC::DFSTOREf32: in expandVSXMemPseudo()
2060 UpperOpcode = PPC::STXSSP; in expandVSXMemPseudo()
2061 LowerOpcode = PPC::STFS; in expandVSXMemPseudo()
2063 case PPC::DFSTOREf64: in expandVSXMemPseudo()
2064 UpperOpcode = PPC::STXSD; in expandVSXMemPseudo()
2065 LowerOpcode = PPC::STFD; in expandVSXMemPseudo()
2067 case PPC::XFLOADf32: in expandVSXMemPseudo()
2068 UpperOpcode = PPC::LXSSPX; in expandVSXMemPseudo()
2069 LowerOpcode = PPC::LFSX; in expandVSXMemPseudo()
2071 case PPC::XFLOADf64: in expandVSXMemPseudo()
2072 UpperOpcode = PPC::LXSDX; in expandVSXMemPseudo()
2073 LowerOpcode = PPC::LFDX; in expandVSXMemPseudo()
2075 case PPC::XFSTOREf32: in expandVSXMemPseudo()
2076 UpperOpcode = PPC::STXSSPX; in expandVSXMemPseudo()
2077 LowerOpcode = PPC::STFSX; in expandVSXMemPseudo()
2079 case PPC::XFSTOREf64: in expandVSXMemPseudo()
2080 UpperOpcode = PPC::STXSDX; in expandVSXMemPseudo()
2081 LowerOpcode = PPC::STFDX; in expandVSXMemPseudo()
2083 case PPC::LIWAX: in expandVSXMemPseudo()
2084 UpperOpcode = PPC::LXSIWAX; in expandVSXMemPseudo()
2085 LowerOpcode = PPC::LFIWAX; in expandVSXMemPseudo()
2087 case PPC::LIWZX: in expandVSXMemPseudo()
2088 UpperOpcode = PPC::LXSIWZX; in expandVSXMemPseudo()
2089 LowerOpcode = PPC::LFIWZX; in expandVSXMemPseudo()
2091 case PPC::STIWX: in expandVSXMemPseudo()
2092 UpperOpcode = PPC::STXSIWX; in expandVSXMemPseudo()
2093 LowerOpcode = PPC::STFIWX; in expandVSXMemPseudo()
2101 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
2102 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
2123 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
2124 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
2130 case PPC::DFLOADf32: in expandPostRAPseudo()
2131 case PPC::DFLOADf64: in expandPostRAPseudo()
2132 case PPC::DFSTOREf32: in expandPostRAPseudo()
2133 case PPC::DFSTOREf64: { in expandPostRAPseudo()
2141 case PPC::XFLOADf32: in expandPostRAPseudo()
2142 case PPC::XFSTOREf32: in expandPostRAPseudo()
2143 case PPC::LIWAX: in expandPostRAPseudo()
2144 case PPC::LIWZX: in expandPostRAPseudo()
2145 case PPC::STIWX: { in expandPostRAPseudo()
2152 case PPC::XFLOADf64: in expandPostRAPseudo()
2153 case PPC::XFSTOREf64: { in expandPostRAPseudo()
2160 case PPC::SPILLTOVSR_LD: { in expandPostRAPseudo()
2162 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
2163 MI.setDesc(get(PPC::DFLOADf64)); in expandPostRAPseudo()
2167 MI.setDesc(get(PPC::LD)); in expandPostRAPseudo()
2170 case PPC::SPILLTOVSR_ST: { in expandPostRAPseudo()
2172 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
2174 MI.setDesc(get(PPC::DFSTOREf64)); in expandPostRAPseudo()
2178 MI.setDesc(get(PPC::STD)); in expandPostRAPseudo()
2182 case PPC::SPILLTOVSR_LDX: { in expandPostRAPseudo()
2184 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
2185 MI.setDesc(get(PPC::LXSDX)); in expandPostRAPseudo()
2187 MI.setDesc(get(PPC::LDX)); in expandPostRAPseudo()
2190 case PPC::SPILLTOVSR_STX: { in expandPostRAPseudo()
2192 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
2194 MI.setDesc(get(PPC::STXSDX)); in expandPostRAPseudo()
2197 MI.setDesc(get(PPC::STDX)); in expandPostRAPseudo()
2202 case PPC::CFENCE8: { in expandPostRAPseudo()
2204 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val); in expandPostRAPseudo()
2205 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP)) in expandPostRAPseudo()
2206 .addImm(PPC::PRED_NE_MINUS) in expandPostRAPseudo()
2207 .addReg(PPC::CR7) in expandPostRAPseudo()
2209 MI.setDesc(get(PPC::ISYNC)); in expandPostRAPseudo()
2225 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) { in selectReg()
2228 case PPC::sub_lt: in selectReg()
2230 case PPC::sub_gt: in selectReg()
2232 case PPC::sub_eq: in selectReg()
2237 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) { in selectReg()
2240 case PPC::sub_lt: in selectReg()
2242 case PPC::sub_gt: in selectReg()
2244 case PPC::sub_eq: in selectReg()
2248 return PPC::NoRegister; in selectReg()
2291 MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo)); in replaceInstrWithLI()
2294 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
2298 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI)); in replaceInstrWithLI()
2325 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) { in getForwardingDefMI()
2338 Opc == PPC::CMPWI || Opc == PPC::CMPLWI || in getForwardingDefMI()
2339 Opc == PPC::CMPDI || Opc == PPC::CMPLDI || in getForwardingDefMI()
2340 Opc == PPC::ADDI || Opc == PPC::ADDI8 || in getForwardingDefMI()
2341 Opc == PPC::ORI || Opc == PPC::ORI8 || in getForwardingDefMI()
2342 Opc == PPC::XORI || Opc == PPC::XORI8 || in getForwardingDefMI()
2343 Opc == PPC::RLDICL || Opc == PPC::RLDICLo || in getForwardingDefMI()
2344 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 || in getForwardingDefMI()
2345 Opc == PPC::RLWINM || Opc == PPC::RLWINMo || in getForwardingDefMI()
2346 Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o; in getForwardingDefMI()
2351 if ((Opc == PPC::OR || Opc == PPC::OR8) && in getForwardingDefMI()
2366 if (PPC::G8RCRegClass.contains(Reg)) in getForwardingDefMI()
2367 Reg = Reg - PPC::X0 + PPC::R0; in getForwardingDefMI()
2375 case PPC::LI: in getForwardingDefMI()
2376 case PPC::LI8: in getForwardingDefMI()
2377 case PPC::ADDItocL: in getForwardingDefMI()
2378 case PPC::ADDI: in getForwardingDefMI()
2379 case PPC::ADDI8: in getForwardingDefMI()
2398 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, in getStoreOpcodesForSpillArray()
2399 PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, in getStoreOpcodesForSpillArray()
2400 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, in getStoreOpcodesForSpillArray()
2401 PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW}, in getStoreOpcodesForSpillArray()
2403 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, in getStoreOpcodesForSpillArray()
2404 PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, in getStoreOpcodesForSpillArray()
2405 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, in getStoreOpcodesForSpillArray()
2406 PPC::SPILLTOVSR_ST}}; in getStoreOpcodesForSpillArray()
2414 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, in getLoadOpcodesForSpillArray()
2415 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, in getLoadOpcodesForSpillArray()
2416 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, in getLoadOpcodesForSpillArray()
2417 PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ}, in getLoadOpcodesForSpillArray()
2419 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, in getLoadOpcodesForSpillArray()
2420 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32, in getLoadOpcodesForSpillArray()
2421 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, in getLoadOpcodesForSpillArray()
2422 PPC::SPILLTOVSR_LD}}; in getLoadOpcodesForSpillArray()
2457 if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) || in convertToImmediateForm()
2483 case PPC::CMPWI: in convertToImmediateForm()
2484 case PPC::CMPLWI: in convertToImmediateForm()
2485 case PPC::CMPDI: in convertToImmediateForm()
2486 case PPC::CMPLDI: { in convertToImmediateForm()
2501 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8) in convertToImmediateForm()
2508 if (RegToCopy == PPC::NoRegister) in convertToImmediateForm()
2511 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) { in convertToImmediateForm()
2512 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI)); in convertToImmediateForm()
2523 CompareUseMI.setDesc(get(PPC::COPY)); in convertToImmediateForm()
2540 case PPC::ADDI: in convertToImmediateForm()
2541 case PPC::ADDI8: { in convertToImmediateForm()
2546 Is64BitLI = Opc == PPC::ADDI8; in convertToImmediateForm()
2552 case PPC::RLDICL: in convertToImmediateForm()
2553 case PPC::RLDICLo: in convertToImmediateForm()
2554 case PPC::RLDICL_32: in convertToImmediateForm()
2555 case PPC::RLDICL_32_64: { in convertToImmediateForm()
2559 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ? in convertToImmediateForm()
2568 (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) { in convertToImmediateForm()
2570 Is64BitLI = Opc != PPC::RLDICL_32; in convertToImmediateForm()
2572 SetCR = Opc == PPC::RLDICLo; in convertToImmediateForm()
2577 case PPC::RLWINM: in convertToImmediateForm()
2578 case PPC::RLWINM8: in convertToImmediateForm()
2579 case PPC::RLWINMo: in convertToImmediateForm()
2580 case PPC::RLWINM8o: { in convertToImmediateForm()
2593 ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) && in convertToImmediateForm()
2597 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o; in convertToImmediateForm()
2599 SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o; in convertToImmediateForm()
2604 case PPC::ORI: in convertToImmediateForm()
2605 case PPC::ORI8: in convertToImmediateForm()
2606 case PPC::XORI: in convertToImmediateForm()
2607 case PPC::XORI8: { in convertToImmediateForm()
2610 if (Opc == PPC::ORI || Opc == PPC::ORI8) in convertToImmediateForm()
2616 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8; in convertToImmediateForm()
2673 return PPC::VFRCRegClass.contains(Reg); in isVFReg()
2691 case PPC::ADD4: in instrHasImmForm()
2692 case PPC::ADD8: in instrHasImmForm()
2698 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8; in instrHasImmForm()
2700 case PPC::ADDC: in instrHasImmForm()
2701 case PPC::ADDC8: in instrHasImmForm()
2707 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8; in instrHasImmForm()
2709 case PPC::ADDCo: in instrHasImmForm()
2715 III.ImmOpcode = PPC::ADDICo; in instrHasImmForm()
2717 case PPC::SUBFC: in instrHasImmForm()
2718 case PPC::SUBFC8: in instrHasImmForm()
2723 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8; in instrHasImmForm()
2725 case PPC::CMPW: in instrHasImmForm()
2726 case PPC::CMPD: in instrHasImmForm()
2731 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI; in instrHasImmForm()
2733 case PPC::CMPLW: in instrHasImmForm()
2734 case PPC::CMPLD: in instrHasImmForm()
2739 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI; in instrHasImmForm()
2741 case PPC::ANDo: in instrHasImmForm()
2742 case PPC::AND8o: in instrHasImmForm()
2743 case PPC::OR: in instrHasImmForm()
2744 case PPC::OR8: in instrHasImmForm()
2745 case PPC::XOR: in instrHasImmForm()
2746 case PPC::XOR8: in instrHasImmForm()
2753 case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break; in instrHasImmForm()
2754 case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break; in instrHasImmForm()
2755 case PPC::OR: III.ImmOpcode = PPC::ORI; break; in instrHasImmForm()
2756 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break; in instrHasImmForm()
2757 case PPC::XOR: III.ImmOpcode = PPC::XORI; break; in instrHasImmForm()
2758 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break; in instrHasImmForm()
2761 case PPC::RLWNM: in instrHasImmForm()
2762 case PPC::RLWNM8: in instrHasImmForm()
2763 case PPC::RLWNMo: in instrHasImmForm()
2764 case PPC::RLWNM8o: in instrHasImmForm()
2765 case PPC::SLW: in instrHasImmForm()
2766 case PPC::SLW8: in instrHasImmForm()
2767 case PPC::SLWo: in instrHasImmForm()
2768 case PPC::SLW8o: in instrHasImmForm()
2769 case PPC::SRW: in instrHasImmForm()
2770 case PPC::SRW8: in instrHasImmForm()
2771 case PPC::SRWo: in instrHasImmForm()
2772 case PPC::SRW8o: in instrHasImmForm()
2773 case PPC::SRAW: in instrHasImmForm()
2774 case PPC::SRAWo: in instrHasImmForm()
2784 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || in instrHasImmForm()
2785 Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o) in instrHasImmForm()
2791 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
2792 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
2793 case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break; in instrHasImmForm()
2794 case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break; in instrHasImmForm()
2795 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
2796 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
2797 case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break; in instrHasImmForm()
2798 case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break; in instrHasImmForm()
2799 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
2800 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
2801 case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break; in instrHasImmForm()
2802 case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break; in instrHasImmForm()
2803 case PPC::SRAW: in instrHasImmForm()
2806 III.ImmOpcode = PPC::SRAWI; in instrHasImmForm()
2808 case PPC::SRAWo: in instrHasImmForm()
2811 III.ImmOpcode = PPC::SRAWIo; in instrHasImmForm()
2815 case PPC::RLDCL: in instrHasImmForm()
2816 case PPC::RLDCLo: in instrHasImmForm()
2817 case PPC::RLDCR: in instrHasImmForm()
2818 case PPC::RLDCRo: in instrHasImmForm()
2819 case PPC::SLD: in instrHasImmForm()
2820 case PPC::SLDo: in instrHasImmForm()
2821 case PPC::SRD: in instrHasImmForm()
2822 case PPC::SRDo: in instrHasImmForm()
2823 case PPC::SRAD: in instrHasImmForm()
2824 case PPC::SRADo: in instrHasImmForm()
2834 if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo || in instrHasImmForm()
2835 Opc == PPC::RLDCR || Opc == PPC::RLDCRo) in instrHasImmForm()
2841 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
2842 case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break; in instrHasImmForm()
2843 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
2844 case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break; in instrHasImmForm()
2845 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
2846 case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break; in instrHasImmForm()
2847 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
2848 case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break; in instrHasImmForm()
2849 case PPC::SRAD: in instrHasImmForm()
2852 III.ImmOpcode = PPC::SRADI; in instrHasImmForm()
2854 case PPC::SRADo: in instrHasImmForm()
2857 III.ImmOpcode = PPC::SRADIo; in instrHasImmForm()
2862 case PPC::LBZX: in instrHasImmForm()
2863 case PPC::LBZX8: in instrHasImmForm()
2864 case PPC::LHZX: in instrHasImmForm()
2865 case PPC::LHZX8: in instrHasImmForm()
2866 case PPC::LHAX: in instrHasImmForm()
2867 case PPC::LHAX8: in instrHasImmForm()
2868 case PPC::LWZX: in instrHasImmForm()
2869 case PPC::LWZX8: in instrHasImmForm()
2870 case PPC::LWAX: in instrHasImmForm()
2871 case PPC::LDX: in instrHasImmForm()
2872 case PPC::LFSX: in instrHasImmForm()
2873 case PPC::LFDX: in instrHasImmForm()
2874 case PPC::STBX: in instrHasImmForm()
2875 case PPC::STBX8: in instrHasImmForm()
2876 case PPC::STHX: in instrHasImmForm()
2877 case PPC::STHX8: in instrHasImmForm()
2878 case PPC::STWX: in instrHasImmForm()
2879 case PPC::STWX8: in instrHasImmForm()
2880 case PPC::STDX: in instrHasImmForm()
2881 case PPC::STFSX: in instrHasImmForm()
2882 case PPC::STFDX: in instrHasImmForm()
2892 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break; in instrHasImmForm()
2893 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break; in instrHasImmForm()
2894 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break; in instrHasImmForm()
2895 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break; in instrHasImmForm()
2896 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break; in instrHasImmForm()
2897 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break; in instrHasImmForm()
2898 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break; in instrHasImmForm()
2899 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break; in instrHasImmForm()
2900 case PPC::LWAX: in instrHasImmForm()
2901 III.ImmOpcode = PPC::LWA; in instrHasImmForm()
2904 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break; in instrHasImmForm()
2905 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break; in instrHasImmForm()
2906 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break; in instrHasImmForm()
2907 case PPC::STBX: III.ImmOpcode = PPC::STB; break; in instrHasImmForm()
2908 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break; in instrHasImmForm()
2909 case PPC::STHX: III.ImmOpcode = PPC::STH; break; in instrHasImmForm()
2910 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break; in instrHasImmForm()
2911 case PPC::STWX: III.ImmOpcode = PPC::STW; break; in instrHasImmForm()
2912 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break; in instrHasImmForm()
2913 case PPC::STDX: in instrHasImmForm()
2914 III.ImmOpcode = PPC::STD; in instrHasImmForm()
2917 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break; in instrHasImmForm()
2918 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break; in instrHasImmForm()
2921 case PPC::LBZUX: in instrHasImmForm()
2922 case PPC::LBZUX8: in instrHasImmForm()
2923 case PPC::LHZUX: in instrHasImmForm()
2924 case PPC::LHZUX8: in instrHasImmForm()
2925 case PPC::LHAUX: in instrHasImmForm()
2926 case PPC::LHAUX8: in instrHasImmForm()
2927 case PPC::LWZUX: in instrHasImmForm()
2928 case PPC::LWZUX8: in instrHasImmForm()
2929 case PPC::LDUX: in instrHasImmForm()
2930 case PPC::LFSUX: in instrHasImmForm()
2931 case PPC::LFDUX: in instrHasImmForm()
2932 case PPC::STBUX: in instrHasImmForm()
2933 case PPC::STBUX8: in instrHasImmForm()
2934 case PPC::STHUX: in instrHasImmForm()
2935 case PPC::STHUX8: in instrHasImmForm()
2936 case PPC::STWUX: in instrHasImmForm()
2937 case PPC::STWUX8: in instrHasImmForm()
2938 case PPC::STDUX: in instrHasImmForm()
2939 case PPC::STFSUX: in instrHasImmForm()
2940 case PPC::STFDUX: in instrHasImmForm()
2950 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break; in instrHasImmForm()
2951 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break; in instrHasImmForm()
2952 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break; in instrHasImmForm()
2953 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break; in instrHasImmForm()
2954 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break; in instrHasImmForm()
2955 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break; in instrHasImmForm()
2956 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break; in instrHasImmForm()
2957 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break; in instrHasImmForm()
2958 case PPC::LDUX: in instrHasImmForm()
2959 III.ImmOpcode = PPC::LDU; in instrHasImmForm()
2962 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break; in instrHasImmForm()
2963 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break; in instrHasImmForm()
2964 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break; in instrHasImmForm()
2965 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break; in instrHasImmForm()
2966 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break; in instrHasImmForm()
2967 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break; in instrHasImmForm()
2968 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break; in instrHasImmForm()
2969 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break; in instrHasImmForm()
2970 case PPC::STDUX: in instrHasImmForm()
2971 III.ImmOpcode = PPC::STDU; in instrHasImmForm()
2974 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break; in instrHasImmForm()
2975 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break; in instrHasImmForm()
2982 case PPC::LXVX: in instrHasImmForm()
2983 case PPC::LXSSPX: in instrHasImmForm()
2984 case PPC::LXSDX: in instrHasImmForm()
2985 case PPC::STXVX: in instrHasImmForm()
2986 case PPC::STXSSPX: in instrHasImmForm()
2987 case PPC::STXSDX: in instrHasImmForm()
2988 case PPC::XFLOADf32: in instrHasImmForm()
2989 case PPC::XFLOADf64: in instrHasImmForm()
2990 case PPC::XFSTOREf32: in instrHasImmForm()
2991 case PPC::XFSTOREf64: in instrHasImmForm()
3004 case PPC::LXVX: in instrHasImmForm()
3005 III.ImmOpcode = PPC::LXV; in instrHasImmForm()
3008 case PPC::LXSSPX: in instrHasImmForm()
3011 III.ImmOpcode = PPC::LXSSP; in instrHasImmForm()
3013 III.ImmOpcode = PPC::LFS; in instrHasImmForm()
3019 case PPC::XFLOADf32: in instrHasImmForm()
3020 III.ImmOpcode = PPC::DFLOADf32; in instrHasImmForm()
3022 case PPC::LXSDX: in instrHasImmForm()
3025 III.ImmOpcode = PPC::LXSD; in instrHasImmForm()
3027 III.ImmOpcode = PPC::LFD; in instrHasImmForm()
3033 case PPC::XFLOADf64: in instrHasImmForm()
3034 III.ImmOpcode = PPC::DFLOADf64; in instrHasImmForm()
3036 case PPC::STXVX: in instrHasImmForm()
3037 III.ImmOpcode = PPC::STXV; in instrHasImmForm()
3040 case PPC::STXSSPX: in instrHasImmForm()
3043 III.ImmOpcode = PPC::STXSSP; in instrHasImmForm()
3045 III.ImmOpcode = PPC::STFS; in instrHasImmForm()
3051 case PPC::XFSTOREf32: in instrHasImmForm()
3052 III.ImmOpcode = PPC::DFSTOREf32; in instrHasImmForm()
3054 case PPC::STXSDX: in instrHasImmForm()
3057 III.ImmOpcode = PPC::STXSD; in instrHasImmForm()
3059 III.ImmOpcode = PPC::STFD; in instrHasImmForm()
3065 case PPC::XFSTOREf64: in instrHasImmForm()
3066 III.ImmOpcode = PPC::DFSTOREf64; in instrHasImmForm()
3140 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO && in isUseMIElgibleForForwarding()
3141 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8) in isUseMIElgibleForForwarding()
3158 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8) in isDefMIElgibleForForwarding()
3193 if (PPC::G8RCRegClass.contains(Reg)) in isRegElgibleForForwarding()
3194 Reg = Reg - PPC::X0 + PPC::R0; in isRegElgibleForForwarding()
3222 if (DefMI.getOpcode() == PPC::ADDItocL) { in isImmElgibleForForwarding()
3332 if (DefMI.getOpcode() == PPC::ADDItocL) in transformToImmFormFedByAdd()
3396 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) && in transformToImmFormFedByLI()
3399 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) && in transformToImmFormFedByLI()
3406 Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo; in transformToImmFormFedByLI()
3408 Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo; in transformToImmFormFedByLI()
3409 bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo || in transformToImmFormFedByLI()
3410 Opc == PPC::SLDo || Opc == PPC::SRDo; in transformToImmFormFedByLI()
3412 Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo; in transformToImmFormFedByLI()
3435 MI.setDesc(get(PPC::COPY)); in transformToImmFormFedByLI()
3480 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
3481 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; in transformToImmFormFedByLI()
3491 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) in updatedRC()
3492 return &PPC::VSRCRegClass; in updatedRC()
3497 return PPC::getRecordFormOpcode(Opcode); in getRecordFormOpcode()
3505 if (Opcode == PPC::LI || Opcode == PPC::LI8 || in isSignExtendingOp()
3506 Opcode == PPC::LIS || Opcode == PPC::LIS8 || in isSignExtendingOp()
3507 Opcode == PPC::SRAW || Opcode == PPC::SRAWo || in isSignExtendingOp()
3508 Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo || in isSignExtendingOp()
3509 Opcode == PPC::LWA || Opcode == PPC::LWAX || in isSignExtendingOp()
3510 Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 || in isSignExtendingOp()
3511 Opcode == PPC::LHA || Opcode == PPC::LHAX || in isSignExtendingOp()
3512 Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 || in isSignExtendingOp()
3513 Opcode == PPC::LBZ || Opcode == PPC::LBZX || in isSignExtendingOp()
3514 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || in isSignExtendingOp()
3515 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || in isSignExtendingOp()
3516 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 || in isSignExtendingOp()
3517 Opcode == PPC::LHZ || Opcode == PPC::LHZX || in isSignExtendingOp()
3518 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || in isSignExtendingOp()
3519 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || in isSignExtendingOp()
3520 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || in isSignExtendingOp()
3521 Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo || in isSignExtendingOp()
3522 Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo || in isSignExtendingOp()
3523 Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 || in isSignExtendingOp()
3524 Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo || in isSignExtendingOp()
3525 Opcode == PPC::SETB || Opcode == PPC::SETB8 || in isSignExtendingOp()
3526 Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 || in isSignExtendingOp()
3527 Opcode == PPC::EXTSB8_32_64) in isSignExtendingOp()
3530 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33) in isSignExtendingOp()
3533 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo || in isSignExtendingOp()
3534 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) && in isSignExtendingOp()
3548 if (Opcode == PPC::LI || Opcode == PPC::LI8 || in isZeroExtendingOp()
3549 Opcode == PPC::LIS || Opcode == PPC::LIS8) { in isZeroExtendingOp()
3557 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo || in isZeroExtendingOp()
3558 Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo || in isZeroExtendingOp()
3559 Opcode == PPC::RLDICL_32_64) && in isZeroExtendingOp()
3563 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) && in isZeroExtendingOp()
3568 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo || in isZeroExtendingOp()
3569 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo || in isZeroExtendingOp()
3570 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in isZeroExtendingOp()
3575 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo || in isZeroExtendingOp()
3576 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo || in isZeroExtendingOp()
3577 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 || in isZeroExtendingOp()
3578 Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo || in isZeroExtendingOp()
3579 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo || in isZeroExtendingOp()
3580 Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || in isZeroExtendingOp()
3581 Opcode == PPC::SLW || Opcode == PPC::SLWo || in isZeroExtendingOp()
3582 Opcode == PPC::SRW || Opcode == PPC::SRWo || in isZeroExtendingOp()
3583 Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || in isZeroExtendingOp()
3584 Opcode == PPC::SLWI || Opcode == PPC::SLWIo || in isZeroExtendingOp()
3585 Opcode == PPC::SRWI || Opcode == PPC::SRWIo || in isZeroExtendingOp()
3586 Opcode == PPC::LWZ || Opcode == PPC::LWZX || in isZeroExtendingOp()
3587 Opcode == PPC::LWZU || Opcode == PPC::LWZUX || in isZeroExtendingOp()
3588 Opcode == PPC::LWBRX || Opcode == PPC::LHBRX || in isZeroExtendingOp()
3589 Opcode == PPC::LHZ || Opcode == PPC::LHZX || in isZeroExtendingOp()
3590 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || in isZeroExtendingOp()
3591 Opcode == PPC::LBZ || Opcode == PPC::LBZX || in isZeroExtendingOp()
3592 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || in isZeroExtendingOp()
3593 Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || in isZeroExtendingOp()
3594 Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 || in isZeroExtendingOp()
3595 Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 || in isZeroExtendingOp()
3596 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || in isZeroExtendingOp()
3597 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || in isZeroExtendingOp()
3598 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || in isZeroExtendingOp()
3599 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 || in isZeroExtendingOp()
3600 Opcode == PPC::ANDIo || Opcode == PPC::ANDISo || in isZeroExtendingOp()
3601 Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo || in isZeroExtendingOp()
3602 Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo || in isZeroExtendingOp()
3603 Opcode == PPC::MFVSRWZ) in isZeroExtendingOp()
3617 if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset) in isTOCSaveMI()
3640 case PPC::COPY: { in isSignOrZeroExtended()
3662 if (SrcReg == PPC::X3) { in isSignOrZeroExtended()
3667 (--II)->getOpcode() == PPC::ADJCALLSTACKUP) { in isSignOrZeroExtended()
3696 case PPC::ANDIo: in isSignOrZeroExtended()
3697 case PPC::ANDISo: in isSignOrZeroExtended()
3698 case PPC::ORI: in isSignOrZeroExtended()
3699 case PPC::ORIS: in isSignOrZeroExtended()
3700 case PPC::XORI: in isSignOrZeroExtended()
3701 case PPC::XORIS: in isSignOrZeroExtended()
3702 case PPC::ANDIo8: in isSignOrZeroExtended()
3703 case PPC::ANDISo8: in isSignOrZeroExtended()
3704 case PPC::ORI8: in isSignOrZeroExtended()
3705 case PPC::ORIS8: in isSignOrZeroExtended()
3706 case PPC::XORI8: in isSignOrZeroExtended()
3707 case PPC::XORIS8: { in isSignOrZeroExtended()
3722 case PPC::OR: in isSignOrZeroExtended()
3723 case PPC::OR8: in isSignOrZeroExtended()
3724 case PPC::ISEL: in isSignOrZeroExtended()
3725 case PPC::PHI: { in isSignOrZeroExtended()
3732 if (MI.getOpcode() == PPC::PHI) { in isSignOrZeroExtended()
3755 case PPC::AND: in isSignOrZeroExtended()
3756 case PPC::AND8: { in isSignOrZeroExtended()