Lines Matching refs:isPPC64
134 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering() local
135 setMinStackArgumentAlignment(isPPC64 ? 8:4); in PPCTargetLowering()
194 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
197 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
200 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
380 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
428 if (isPPC64) { in PPCTargetLowering()
447 if (Subtarget.isSVR4ABI() && !isPPC64) in PPCTargetLowering()
505 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) in PPCTargetLowering()
706 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
1035 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
1037 if (!isPPC64) { in PPCTargetLowering()
1049 if (!isPPC64) { in PPCTargetLowering()
1056 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1); in PPCTargetLowering()
1229 unsigned Align = Subtarget.isPPC64() ? 8 : 4; in getByValTypeAlignment()
2354 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2411 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
2610 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerConstantPool()
2644 if (Subtarget.isPPC64()) in isJumpTableRelative()
2651 if (!Subtarget.isPPC64()) in getPICJumpTableRelocBase()
2668 if (!Subtarget.isPPC64()) in getPICJumpTableRelocBaseExpr()
2686 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerJumpTable()
2716 (Subtarget.isPPC64() || isPositionIndependent())) { in LowerBlockAddress()
2717 if (Subtarget.isPPC64()) in LowerBlockAddress()
2720 return getTOCEntry(DAG, SDLoc(BASDN), Subtarget.isPPC64(), GA); in LowerBlockAddress()
2744 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddress()
2830 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerGlobalAddress()
2924 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
3015 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
3039 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE() local
3049 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl, in LowerINIT_TRAMPOLINE()
3050 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
3073 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { in LowerVASTART()
3388 if (Subtarget.isPPC64()) in LowerFormalArguments()
4080 bool isPPC64 = PtrVT == MVT::i64; in LowerFormalArguments_Darwin() local
4084 unsigned PtrByteSize = isPPC64 ? 8 : 4; in LowerFormalArguments_Darwin()
4109 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin()
4119 if (!isVarArg && !isPPC64) { in LowerFormalArguments_Darwin()
4185 if (isVarArg || isPPC64) { in LowerFormalArguments_Darwin()
4217 if (isPPC64) in LowerFormalArguments_Darwin()
4240 if (isPPC64) in LowerFormalArguments_Darwin()
4264 if (!isPPC64) { in LowerFormalArguments_Darwin()
4307 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) in LowerFormalArguments_Darwin()
4325 ArgOffset += isPPC64 ? 8 : ObjSize; in LowerFormalArguments_Darwin()
4347 if (!isVarArg && !isPPC64) { in LowerFormalArguments_Darwin()
4408 if (isPPC64) in LowerFormalArguments_Darwin()
4509 assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64()); in needStackSlotPassParameters()
4765 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr() local
4766 int SlotSize = isPPC64 ? 8 : 4; in EmitTailCallStoreFPAndRetAddr()
4770 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
4793 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, in CalculateTailCallArgDest() argument
4799 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
4816 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
4851 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, in LowerMemOpCallTo() argument
4858 if (isPPC64) in LowerMemOpCallTo()
4868 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, in LowerMemOpCallTo()
4917 bool isPPC64 = Subtarget.isPPC64(); in PrepareCall() local
4928 if (!isSVR4ABI || !isPPC64) in PrepareCall()
4944 bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64; in PrepareCall()
4988 if (isSVR4ABI && isPPC64 && !isELFv2ABI) { in PrepareCall()
5076 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest) in PrepareCall()
5080 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); in PrepareCall()
5101 if (isSVR4ABI && isPPC64) { in PrepareCall()
5175 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64()) in FinishCall()
5218 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() && in FinishCall()
5280 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in LowerCall()
5318 if (Subtarget.isPPC64()) in LowerCall()
6245 bool isPPC64 = PtrVT == MVT::i64; in LowerCall_Darwin() local
6246 unsigned PtrByteSize = isPPC64 ? 8 : 4; in LowerCall_Darwin()
6279 if (!isVarArg && !isPPC64) { in LowerCall_Darwin()
6332 if (isPPC64) in LowerCall_Darwin()
6360 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin()
6379 if (isPPC64 && Arg.getValueType() == MVT::i32) { in LowerCall_Darwin()
6451 isPPC64, isTailCall, false, MemOpChains, in LowerCall_Darwin()
6473 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ in LowerCall_Darwin()
6488 !isPPC64) // PPC64 has 64-bit GPR's obviously :) in LowerCall_Darwin()
6493 isPPC64, isTailCall, false, MemOpChains, in LowerCall_Darwin()
6495 if (isPPC64) in LowerCall_Darwin()
6550 isPPC64, isTailCall, true, MemOpChains, in LowerCall_Darwin()
6576 isPPC64, isTailCall, true, MemOpChains, in LowerCall_Darwin()
6594 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : in LowerCall_Darwin()
6726 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE() local
6727 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; in LowerSTACKRESTORE()
6747 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex() local
6760 RASI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, LROffset, false); in getReturnAddrFrameIndex()
6770 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex() local
6783 FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); in getFramePointerFrameIndex()
6814 bool isPPC64 = Subtarget.isPPC64(); in LowerEH_DWARF_CFA() local
6817 int FI = MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, 0, false); in LowerEH_DWARF_CFA()
7143 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
7400 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
7582 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
9028 if (Subtarget.isPPC64()) in LowerINTRINSIC_WO_CHAIN()
9105 assert(Subtarget.isPPC64() && "Only 64-bit is supported for now."); in LowerINTRINSIC_VOID()
9720 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
9775 if (isa<LoadInst>(Inst) && Subtarget.isPPC64()) in emitTrailingFence()
9921 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
10171 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) { in emitEHSjLjSetJmp()
10184 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
10186 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
10189 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
10212 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
10215 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
10348 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() && in EmitInstrWithCustomInserter()
10739 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
11668 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
12712 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
12747 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
13160 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && in PerformDAGCombine()
13373 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
13576 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
13580 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
13638 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
13784 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR() local
13791 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
13813 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR() local
13819 FrameReg = isPPC64 ? PPC::X1 : PPC::R1; in LowerFRAMEADDR()
13821 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; in LowerFRAMEADDR()
13835 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName() local
13838 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) || in getRegisterByName()
13839 (!isPPC64 && VT != MVT::i32)) in getRegisterByName()
13842 bool is64Bit = isPPC64 && VT == MVT::i64; in getRegisterByName()
13845 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2) in getRegisterByName()
13846 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 : in getRegisterByName()
13857 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64()) in isAccessedAsGotIndirect()
14108 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
14147 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
14247 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
14252 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
14283 if (!Subtarget.isPPC64()) return; in initializeSplitCSR()
14448 if (!Subtarget.isPPC64()) in combineADDToADDZE()
14590 if (!Subtarget.isSVR4ABI() || !Subtarget.isPPC64()) in mayBeEmittedAsTailCall()