Lines Matching refs:MVT
138 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
141 addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass); in PPCTargetLowering()
142 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
144 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
145 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
150 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
151 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
154 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); in PPCTargetLowering()
157 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
158 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
159 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in PPCTargetLowering()
162 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
165 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
166 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
167 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
168 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
169 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
170 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
171 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
172 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
173 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
174 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
176 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
177 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
178 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
179 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
183 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in PPCTargetLowering()
184 for (MVT VT : ScalarIntVTs) { in PPCTargetLowering()
192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
195 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
196 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
197 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
198 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
199 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
200 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
202 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
203 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
207 setOperationAction(ISD::LOAD, MVT::i1, Custom); in PPCTargetLowering()
208 setOperationAction(ISD::STORE, MVT::i1, Custom); in PPCTargetLowering()
212 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in PPCTargetLowering()
214 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
215 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
216 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
217 setTruncStoreAction(VT, MVT::i1, Expand); in PPCTargetLowering()
220 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
225 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom); in PPCTargetLowering()
226 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom); in PPCTargetLowering()
229 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
230 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
231 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); in PPCTargetLowering()
232 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); in PPCTargetLowering()
233 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
234 setOperationAction(ISD::FREM, MVT::ppcf128, Expand); in PPCTargetLowering()
243 setOperationAction(ISD::SREM, MVT::i32, Custom); in PPCTargetLowering()
244 setOperationAction(ISD::UREM, MVT::i32, Custom); in PPCTargetLowering()
245 setOperationAction(ISD::SREM, MVT::i64, Custom); in PPCTargetLowering()
246 setOperationAction(ISD::UREM, MVT::i64, Custom); in PPCTargetLowering()
248 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
249 setOperationAction(ISD::UREM, MVT::i32, Expand); in PPCTargetLowering()
250 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
251 setOperationAction(ISD::UREM, MVT::i64, Expand); in PPCTargetLowering()
255 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
256 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
257 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
258 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
259 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in PPCTargetLowering()
260 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in PPCTargetLowering()
261 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in PPCTargetLowering()
262 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in PPCTargetLowering()
265 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
266 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
267 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in PPCTargetLowering()
268 setOperationAction(ISD::FREM , MVT::f64, Expand); in PPCTargetLowering()
269 setOperationAction(ISD::FPOW , MVT::f64, Expand); in PPCTargetLowering()
270 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
271 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
272 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in PPCTargetLowering()
273 setOperationAction(ISD::FREM , MVT::f32, Expand); in PPCTargetLowering()
274 setOperationAction(ISD::FPOW , MVT::f32, Expand); in PPCTargetLowering()
276 setOperationAction(ISD::FMA , MVT::f64, Expand); in PPCTargetLowering()
277 setOperationAction(ISD::FMA , MVT::f32, Expand); in PPCTargetLowering()
279 setOperationAction(ISD::FMA , MVT::f64, Legal); in PPCTargetLowering()
280 setOperationAction(ISD::FMA , MVT::f32, Legal); in PPCTargetLowering()
283 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); in PPCTargetLowering()
289 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
294 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
297 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
298 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
300 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
301 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
305 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
306 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
307 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
308 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
310 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
311 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
312 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
313 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
319 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); in PPCTargetLowering()
321 setOperationAction(ISD::BSWAP, MVT::i64 , Custom); in PPCTargetLowering()
323 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); in PPCTargetLowering()
325 setOperationAction(ISD::CTTZ , MVT::i32 , Legal); in PPCTargetLowering()
326 setOperationAction(ISD::CTTZ , MVT::i64 , Legal); in PPCTargetLowering()
328 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); in PPCTargetLowering()
329 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in PPCTargetLowering()
333 setOperationAction(ISD::CTPOP, MVT::i32 , Legal); in PPCTargetLowering()
334 setOperationAction(ISD::CTPOP, MVT::i64 , Legal); in PPCTargetLowering()
336 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); in PPCTargetLowering()
337 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); in PPCTargetLowering()
341 setOperationAction(ISD::ROTR, MVT::i32 , Expand); in PPCTargetLowering()
342 setOperationAction(ISD::ROTR, MVT::i64 , Expand); in PPCTargetLowering()
346 setOperationAction(ISD::SELECT, MVT::i32, Expand); in PPCTargetLowering()
347 setOperationAction(ISD::SELECT, MVT::i64, Expand); in PPCTargetLowering()
348 setOperationAction(ISD::SELECT, MVT::f32, Expand); in PPCTargetLowering()
349 setOperationAction(ISD::SELECT, MVT::f64, Expand); in PPCTargetLowering()
353 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
354 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
358 setOperationAction(ISD::SETCC, MVT::i32, Custom); in PPCTargetLowering()
362 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in PPCTargetLowering()
364 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in PPCTargetLowering()
368 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
369 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
370 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
373 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
376 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
377 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
381 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in PPCTargetLowering()
382 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in PPCTargetLowering()
383 setOperationAction(ISD::BITCAST, MVT::i64, Legal); in PPCTargetLowering()
384 setOperationAction(ISD::BITCAST, MVT::f64, Legal); in PPCTargetLowering()
386 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in PPCTargetLowering()
387 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in PPCTargetLowering()
388 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in PPCTargetLowering()
389 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in PPCTargetLowering()
393 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
401 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); in PPCTargetLowering()
402 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); in PPCTargetLowering()
406 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in PPCTargetLowering()
407 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in PPCTargetLowering()
408 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in PPCTargetLowering()
409 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in PPCTargetLowering()
410 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in PPCTargetLowering()
411 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in PPCTargetLowering()
412 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in PPCTargetLowering()
413 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); in PPCTargetLowering()
414 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); in PPCTargetLowering()
415 setOperationAction(ISD::JumpTable, MVT::i64, Custom); in PPCTargetLowering()
418 setOperationAction(ISD::TRAP, MVT::Other, Legal); in PPCTargetLowering()
421 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
422 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
425 setOperationAction(ISD::VASTART , MVT::Other, Custom); in PPCTargetLowering()
430 setOperationAction(ISD::VAARG, MVT::i1, Promote); in PPCTargetLowering()
431 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); in PPCTargetLowering()
432 setOperationAction(ISD::VAARG, MVT::i8, Promote); in PPCTargetLowering()
433 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); in PPCTargetLowering()
434 setOperationAction(ISD::VAARG, MVT::i16, Promote); in PPCTargetLowering()
435 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); in PPCTargetLowering()
436 setOperationAction(ISD::VAARG, MVT::i32, Promote); in PPCTargetLowering()
437 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); in PPCTargetLowering()
438 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
441 setOperationAction(ISD::VAARG, MVT::Other, Custom); in PPCTargetLowering()
442 setOperationAction(ISD::VAARG, MVT::i64, Custom); in PPCTargetLowering()
445 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
449 setOperationAction(ISD::VACOPY , MVT::Other, Custom); in PPCTargetLowering()
451 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in PPCTargetLowering()
454 setOperationAction(ISD::VAEND , MVT::Other, Expand); in PPCTargetLowering()
455 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in PPCTargetLowering()
456 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); in PPCTargetLowering()
457 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in PPCTargetLowering()
458 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); in PPCTargetLowering()
459 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom); in PPCTargetLowering()
460 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom); in PPCTargetLowering()
461 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); in PPCTargetLowering()
462 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); in PPCTargetLowering()
465 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in PPCTargetLowering()
468 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); in PPCTargetLowering()
470 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom); in PPCTargetLowering()
471 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom); in PPCTargetLowering()
472 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom); in PPCTargetLowering()
473 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in PPCTargetLowering()
477 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in PPCTargetLowering()
478 setCondCodeAction(ISD::SETO, MVT::f64, Expand); in PPCTargetLowering()
479 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in PPCTargetLowering()
480 setCondCodeAction(ISD::SETUO, MVT::f64, Expand); in PPCTargetLowering()
482 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in PPCTargetLowering()
483 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); in PPCTargetLowering()
484 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in PPCTargetLowering()
485 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in PPCTargetLowering()
486 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
487 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
488 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
489 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
490 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in PPCTargetLowering()
491 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in PPCTargetLowering()
492 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in PPCTargetLowering()
493 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); in PPCTargetLowering()
497 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
498 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
499 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
500 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
503 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
506 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
510 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); in PPCTargetLowering()
512 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); in PPCTargetLowering()
518 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
519 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in PPCTargetLowering()
520 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
521 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
524 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
525 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
526 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
527 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
532 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
534 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
536 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
537 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); in PPCTargetLowering()
538 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
541 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
542 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in PPCTargetLowering()
543 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
549 for (MVT VT : MVT::vector_valuetypes()) { in PPCTargetLowering()
556 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
566 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128)) in PPCTargetLowering()
573 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
577 AddPromotedToType (ISD::AND , VT, MVT::v4i32); in PPCTargetLowering()
579 AddPromotedToType (ISD::OR , VT, MVT::v4i32); in PPCTargetLowering()
581 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); in PPCTargetLowering()
583 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); in PPCTargetLowering()
585 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); in PPCTargetLowering()
588 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); in PPCTargetLowering()
590 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); in PPCTargetLowering()
631 for (MVT InnerVT : MVT::vector_valuetypes()) { in PPCTargetLowering()
641 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
643 setOperationAction(ISD::AND , MVT::v4i32, Legal); in PPCTargetLowering()
644 setOperationAction(ISD::OR , MVT::v4i32, Legal); in PPCTargetLowering()
645 setOperationAction(ISD::XOR , MVT::v4i32, Legal); in PPCTargetLowering()
646 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); in PPCTargetLowering()
647 setOperationAction(ISD::SELECT, MVT::v4i32, in PPCTargetLowering()
649 setOperationAction(ISD::STORE , MVT::v4i32, Legal); in PPCTargetLowering()
650 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
651 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
652 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
653 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
654 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
655 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
656 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
657 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
662 setOperationAction(ISD::ABS, MVT::v2i64, Expand); in PPCTargetLowering()
664 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
665 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
666 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
667 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
669 setOperationAction(ISD::MUL, MVT::v4f32, Legal); in PPCTargetLowering()
670 setOperationAction(ISD::FMA, MVT::v4f32, Legal); in PPCTargetLowering()
673 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
674 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
678 setOperationAction(ISD::MUL, MVT::v4i32, Legal); in PPCTargetLowering()
680 setOperationAction(ISD::MUL, MVT::v4i32, Custom); in PPCTargetLowering()
682 setOperationAction(ISD::MUL, MVT::v8i16, Custom); in PPCTargetLowering()
683 setOperationAction(ISD::MUL, MVT::v16i8, Custom); in PPCTargetLowering()
685 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
686 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
688 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); in PPCTargetLowering()
689 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); in PPCTargetLowering()
690 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
691 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
694 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); in PPCTargetLowering()
695 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
696 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); in PPCTargetLowering()
697 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); in PPCTargetLowering()
700 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
701 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
703 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
704 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal); in PPCTargetLowering()
707 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
708 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); in PPCTargetLowering()
709 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); in PPCTargetLowering()
710 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); in PPCTargetLowering()
711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
712 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
713 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
714 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
716 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
718 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
719 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
720 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
721 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
722 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
724 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
726 setOperationAction(ISD::MUL, MVT::v2f64, Legal); in PPCTargetLowering()
727 setOperationAction(ISD::FMA, MVT::v2f64, Legal); in PPCTargetLowering()
729 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
730 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
733 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand); in PPCTargetLowering()
734 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); in PPCTargetLowering()
735 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); in PPCTargetLowering()
736 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand); in PPCTargetLowering()
738 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); in PPCTargetLowering()
739 setOperationAction(ISD::STORE, MVT::v2f64, Legal); in PPCTargetLowering()
741 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal); in PPCTargetLowering()
744 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass); in PPCTargetLowering()
746 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass); in PPCTargetLowering()
748 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass); in PPCTargetLowering()
749 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass); in PPCTargetLowering()
750 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass); in PPCTargetLowering()
753 setOperationAction(ISD::SHL, MVT::v2i64, Legal); in PPCTargetLowering()
754 setOperationAction(ISD::SRA, MVT::v2i64, Legal); in PPCTargetLowering()
755 setOperationAction(ISD::SRL, MVT::v2i64, Legal); in PPCTargetLowering()
761 setOperationAction(ISD::SHL, MVT::v1i128, Expand); in PPCTargetLowering()
762 setOperationAction(ISD::SRL, MVT::v1i128, Expand); in PPCTargetLowering()
763 setOperationAction(ISD::SRA, MVT::v1i128, Expand); in PPCTargetLowering()
765 setOperationAction(ISD::SETCC, MVT::v2i64, Legal); in PPCTargetLowering()
768 setOperationAction(ISD::SHL, MVT::v2i64, Expand); in PPCTargetLowering()
769 setOperationAction(ISD::SRA, MVT::v2i64, Expand); in PPCTargetLowering()
770 setOperationAction(ISD::SRL, MVT::v2i64, Expand); in PPCTargetLowering()
772 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in PPCTargetLowering()
775 setOperationAction(ISD::ADD, MVT::v2i64, Expand); in PPCTargetLowering()
776 setOperationAction(ISD::SUB, MVT::v2i64, Expand); in PPCTargetLowering()
779 setOperationAction(ISD::LOAD, MVT::v2i64, Promote); in PPCTargetLowering()
780 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
781 setOperationAction(ISD::STORE, MVT::v2i64, Promote); in PPCTargetLowering()
782 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal); in PPCTargetLowering()
786 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
787 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
788 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
789 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal); in PPCTargetLowering()
794 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
795 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
796 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
798 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
799 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
800 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
801 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
803 setOperationAction(ISD::FNEG, MVT::v4f32, Legal); in PPCTargetLowering()
804 setOperationAction(ISD::FNEG, MVT::v2f64, Legal); in PPCTargetLowering()
805 setOperationAction(ISD::FABS, MVT::v4f32, Legal); in PPCTargetLowering()
806 setOperationAction(ISD::FABS, MVT::v2f64, Legal); in PPCTargetLowering()
809 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); in PPCTargetLowering()
810 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); in PPCTargetLowering()
812 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); in PPCTargetLowering()
816 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass); in PPCTargetLowering()
817 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass); in PPCTargetLowering()
821 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in PPCTargetLowering()
822 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in PPCTargetLowering()
827 setOperationAction(ISD::SHL, MVT::v1i128, Legal); in PPCTargetLowering()
828 setOperationAction(ISD::SRL, MVT::v1i128, Legal); in PPCTargetLowering()
829 setOperationAction(ISD::SRA, MVT::v1i128, Expand); in PPCTargetLowering()
832 addRegisterClass(MVT::f128, &PPC::VRRCRegClass); in PPCTargetLowering()
833 setOperationAction(ISD::FADD, MVT::f128, Legal); in PPCTargetLowering()
834 setOperationAction(ISD::FSUB, MVT::f128, Legal); in PPCTargetLowering()
835 setOperationAction(ISD::FDIV, MVT::f128, Legal); in PPCTargetLowering()
836 setOperationAction(ISD::FMUL, MVT::f128, Legal); in PPCTargetLowering()
837 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in PPCTargetLowering()
839 for (MVT FPT : MVT::fp_valuetypes()) in PPCTargetLowering()
840 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); in PPCTargetLowering()
841 setOperationAction(ISD::FMA, MVT::f128, Legal); in PPCTargetLowering()
842 setCondCodeAction(ISD::SETULT, MVT::f128, Expand); in PPCTargetLowering()
843 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand); in PPCTargetLowering()
844 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand); in PPCTargetLowering()
845 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand); in PPCTargetLowering()
846 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand); in PPCTargetLowering()
847 setCondCodeAction(ISD::SETONE, MVT::f128, Expand); in PPCTargetLowering()
849 setOperationAction(ISD::FTRUNC, MVT::f128, Legal); in PPCTargetLowering()
850 setOperationAction(ISD::FRINT, MVT::f128, Legal); in PPCTargetLowering()
851 setOperationAction(ISD::FFLOOR, MVT::f128, Legal); in PPCTargetLowering()
852 setOperationAction(ISD::FCEIL, MVT::f128, Legal); in PPCTargetLowering()
853 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
854 setOperationAction(ISD::FROUND, MVT::f128, Legal); in PPCTargetLowering()
856 setOperationAction(ISD::SELECT, MVT::f128, Expand); in PPCTargetLowering()
857 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
858 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
859 setTruncStoreAction(MVT::f128, MVT::f64, Expand); in PPCTargetLowering()
860 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in PPCTargetLowering()
861 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in PPCTargetLowering()
863 setOperationAction(ISD::FSIN , MVT::f128, Expand); in PPCTargetLowering()
864 setOperationAction(ISD::FCOS , MVT::f128, Expand); in PPCTargetLowering()
865 setOperationAction(ISD::FPOW, MVT::f128, Expand); in PPCTargetLowering()
866 setOperationAction(ISD::FPOWI, MVT::f128, Expand); in PPCTargetLowering()
867 setOperationAction(ISD::FREM, MVT::f128, Expand); in PPCTargetLowering()
873 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in PPCTargetLowering()
874 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in PPCTargetLowering()
879 setOperationAction(ISD::FADD, MVT::v4f64, Legal); in PPCTargetLowering()
880 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); in PPCTargetLowering()
881 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); in PPCTargetLowering()
882 setOperationAction(ISD::FREM, MVT::v4f64, Expand); in PPCTargetLowering()
884 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal); in PPCTargetLowering()
885 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
887 setOperationAction(ISD::LOAD , MVT::v4f64, Custom); in PPCTargetLowering()
888 setOperationAction(ISD::STORE , MVT::v4f64, Custom); in PPCTargetLowering()
890 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
891 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
894 setOperationAction(ISD::SELECT, MVT::v4f64, Expand); in PPCTargetLowering()
895 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); in PPCTargetLowering()
897 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal); in PPCTargetLowering()
898 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand); in PPCTargetLowering()
899 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); in PPCTargetLowering()
900 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand); in PPCTargetLowering()
901 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom); in PPCTargetLowering()
902 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal); in PPCTargetLowering()
903 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); in PPCTargetLowering()
905 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal); in PPCTargetLowering()
906 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand); in PPCTargetLowering()
908 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
909 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand); in PPCTargetLowering()
910 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal); in PPCTargetLowering()
912 setOperationAction(ISD::FNEG , MVT::v4f64, Legal); in PPCTargetLowering()
913 setOperationAction(ISD::FABS , MVT::v4f64, Legal); in PPCTargetLowering()
914 setOperationAction(ISD::FSIN , MVT::v4f64, Expand); in PPCTargetLowering()
915 setOperationAction(ISD::FCOS , MVT::v4f64, Expand); in PPCTargetLowering()
916 setOperationAction(ISD::FPOW , MVT::v4f64, Expand); in PPCTargetLowering()
917 setOperationAction(ISD::FLOG , MVT::v4f64, Expand); in PPCTargetLowering()
918 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand); in PPCTargetLowering()
919 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand); in PPCTargetLowering()
920 setOperationAction(ISD::FEXP , MVT::v4f64, Expand); in PPCTargetLowering()
921 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand); in PPCTargetLowering()
923 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal); in PPCTargetLowering()
924 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal); in PPCTargetLowering()
926 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal); in PPCTargetLowering()
927 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal); in PPCTargetLowering()
929 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass); in PPCTargetLowering()
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal); in PPCTargetLowering()
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); in PPCTargetLowering()
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); in PPCTargetLowering()
934 setOperationAction(ISD::FREM, MVT::v4f32, Expand); in PPCTargetLowering()
936 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
937 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand); in PPCTargetLowering()
939 setOperationAction(ISD::LOAD , MVT::v4f32, Custom); in PPCTargetLowering()
940 setOperationAction(ISD::STORE , MVT::v4f32, Custom); in PPCTargetLowering()
943 setOperationAction(ISD::SELECT, MVT::v4f32, Expand); in PPCTargetLowering()
944 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
946 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal); in PPCTargetLowering()
947 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand); in PPCTargetLowering()
948 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand); in PPCTargetLowering()
949 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand); in PPCTargetLowering()
950 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom); in PPCTargetLowering()
951 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
952 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
954 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal); in PPCTargetLowering()
955 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand); in PPCTargetLowering()
957 setOperationAction(ISD::FNEG , MVT::v4f32, Legal); in PPCTargetLowering()
958 setOperationAction(ISD::FABS , MVT::v4f32, Legal); in PPCTargetLowering()
959 setOperationAction(ISD::FSIN , MVT::v4f32, Expand); in PPCTargetLowering()
960 setOperationAction(ISD::FCOS , MVT::v4f32, Expand); in PPCTargetLowering()
961 setOperationAction(ISD::FPOW , MVT::v4f32, Expand); in PPCTargetLowering()
962 setOperationAction(ISD::FLOG , MVT::v4f32, Expand); in PPCTargetLowering()
963 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand); in PPCTargetLowering()
964 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand); in PPCTargetLowering()
965 setOperationAction(ISD::FEXP , MVT::v4f32, Expand); in PPCTargetLowering()
966 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand); in PPCTargetLowering()
968 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
969 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in PPCTargetLowering()
971 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal); in PPCTargetLowering()
972 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal); in PPCTargetLowering()
974 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass); in PPCTargetLowering()
976 setOperationAction(ISD::AND , MVT::v4i1, Legal); in PPCTargetLowering()
977 setOperationAction(ISD::OR , MVT::v4i1, Legal); in PPCTargetLowering()
978 setOperationAction(ISD::XOR , MVT::v4i1, Legal); in PPCTargetLowering()
981 setOperationAction(ISD::SELECT, MVT::v4i1, Expand); in PPCTargetLowering()
982 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal); in PPCTargetLowering()
984 setOperationAction(ISD::LOAD , MVT::v4i1, Custom); in PPCTargetLowering()
985 setOperationAction(ISD::STORE , MVT::v4i1, Custom); in PPCTargetLowering()
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom); in PPCTargetLowering()
988 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand); in PPCTargetLowering()
989 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); in PPCTargetLowering()
990 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand); in PPCTargetLowering()
991 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom); in PPCTargetLowering()
992 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand); in PPCTargetLowering()
993 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom); in PPCTargetLowering()
995 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom); in PPCTargetLowering()
996 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom); in PPCTargetLowering()
998 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass); in PPCTargetLowering()
1000 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); in PPCTargetLowering()
1001 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in PPCTargetLowering()
1002 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal); in PPCTargetLowering()
1003 setOperationAction(ISD::FROUND, MVT::v4f64, Legal); in PPCTargetLowering()
1005 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
1006 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
1007 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
1008 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
1010 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand); in PPCTargetLowering()
1011 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in PPCTargetLowering()
1014 setOperationAction(ISD::FRINT, MVT::v4f64, Expand); in PPCTargetLowering()
1015 setOperationAction(ISD::FRINT, MVT::v4f32, Expand); in PPCTargetLowering()
1018 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); in PPCTargetLowering()
1019 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in PPCTargetLowering()
1021 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
1022 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
1024 setOperationAction(ISD::FDIV, MVT::v4f64, Expand); in PPCTargetLowering()
1025 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); in PPCTargetLowering()
1027 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in PPCTargetLowering()
1028 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in PPCTargetLowering()
1033 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); in PPCTargetLowering()
1035 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
1038 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); in PPCTargetLowering()
1039 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); in PPCTargetLowering()
1238 if (Subtarget.hasSPE() && VT == MVT::f64) in getNumRegistersForCallingConv()
1243 MVT PPCTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, in getRegisterTypeForCallingConv()
1246 if (Subtarget.hasSPE() && VT == MVT::f64) in getRegisterTypeForCallingConv()
1247 return MVT::i32; in getRegisterTypeForCallingConv()
1376 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1379 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements()); in getSetCCResultType()
1532 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
1642 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
1700 if (N->getValueType(0) != MVT::v16i8) in isVSLDOIShuffleMask()
1743 assert(N->getValueType(0) == MVT::v16i8 && in isSplatShuffleMask()
1887 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXSLDWIShuffleMask()
1948 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXBRShuffleMaskHelper()
1986 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXPERMDIShuffleMask()
2095 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef in get_VSPLTI_elt()
2098 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2102 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef in get_VSPLTI_elt()
2105 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2127 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); in get_VSPLTI_elt()
2149 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2157 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1) in isQVALIGNIShuffleMask()
2196 if (N->getValueType(0) == MVT::i32) in isIntS16Immediate()
2255 if (VT != MVT::i64) in fixupFuncForFI()
2360 if ((CN->getValueType(0) == MVT::i32 || in SelectAddressRegImm()
2366 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32); in SelectAddressRegImm()
2369 MVT::i32); in SelectAddressRegImm()
2370 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectAddressRegImm()
2429 if (MemVT.isSimple() && MemVT.getSimpleVT().SimpleTy == MVT::i64) { in usePartialVectorLoads()
2474 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) { in getPreIndexedAddressParts()
2505 if (VT != MVT::i64) { in getPreIndexedAddressParts()
2520 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && in getPreIndexedAddressParts()
2591 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; in getTOCEntry()
2597 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT, in getTOCEntry()
2755 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64) in LowerGlobalTLSAddress()
2756 : DAG.getRegister(PPC::R2, MVT::i32); in LowerGlobalTLSAddress()
2769 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
2784 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
2802 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
2865 if (Op.getValueType() == MVT::v2i64) { in LowerSETCC()
2868 if (Op.getOperand(0).getValueType() == MVT::v2i64) { in LowerSETCC()
2872 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, in LowerSETCC()
2873 DAG.getSetCC(dl, MVT::v4i32, in LowerSETCC()
2874 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)), in LowerSETCC()
2875 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)), in LowerSETCC()
2927 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
2928 VAListPtr, MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
2931 if (VT == MVT::i64) { in LowerVAARG()
2933 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, in LowerVAARG()
2934 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
2935 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, in LowerVAARG()
2936 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE); in LowerVAARG()
2937 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, in LowerVAARG()
2938 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
2940 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, in LowerVAARG()
2946 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
2949 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
2950 FprPtr, MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
2954 DAG.getConstant(8, dl, MVT::i32)); in LowerVAARG()
2957 DAG.getConstant(4, dl, MVT::i32)); in LowerVAARG()
2961 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo()); in LowerVAARG()
2965 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo()); in LowerVAARG()
2969 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, in LowerVAARG()
2970 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT); in LowerVAARG()
2973 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, in LowerVAARG()
2976 MVT::i32)); in LowerVAARG()
2985 DAG.getConstant(32, dl, MVT::i32)); in LowerVAARG()
2988 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, in LowerVAARG()
2990 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl, in LowerVAARG()
2991 MVT::i32)); in LowerVAARG()
2995 MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
3003 dl, MVT::i32)); in LowerVAARG()
3005 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, in LowerVAARG()
3009 MachinePointerInfo(), MVT::i32); in LowerVAARG()
3021 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true, in LowerVACOPY()
3039 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE()
3050 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
3106 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32); in LowerVASTART()
3107 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32); in LowerVASTART()
3127 MachinePointerInfo(SV), MVT::i8); in LowerVASTART()
3135 MachinePointerInfo(SV, nextOffset), MVT::i8); in LowerVASTART()
3158 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_PPC32_SVR4_Custom_Dummy()
3165 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, in CC_PPC32_SVR4_Custom_AlignArgRegs()
3166 MVT &LocVT, in CC_PPC32_SVR4_Custom_AlignArgRegs()
3193 llvm::CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
3194 MVT &LocVT, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
3218 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
3219 MVT &LocVT, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
3280 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotAlignment()
3281 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotAlignment()
3282 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotAlignment()
3283 ArgVT == MVT::v1i128 || ArgVT == MVT::f128) in CalculateStackSlotAlignment()
3287 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1) in CalculateStackSlotAlignment()
3307 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
3351 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 || in CalculateStackSlotUsed()
3353 (HasQPX && (ArgVT == MVT::v4f32 || in CalculateStackSlotUsed()
3354 ArgVT == MVT::v4f64 || in CalculateStackSlotUsed()
3355 ArgVT == MVT::v4i1))) in CalculateStackSlotUsed()
3360 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotUsed()
3361 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotUsed()
3362 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotUsed()
3363 ArgVT == MVT::v1i128 || ArgVT == MVT::f128) in CalculateStackSlotUsed()
3469 case MVT::i1: in LowerFormalArguments_32SVR4()
3470 case MVT::i32: in LowerFormalArguments_32SVR4()
3473 case MVT::f32: in LowerFormalArguments_32SVR4()
3481 case MVT::f64: in LowerFormalArguments_32SVR4()
3489 case MVT::v16i8: in LowerFormalArguments_32SVR4()
3490 case MVT::v8i16: in LowerFormalArguments_32SVR4()
3491 case MVT::v4i32: in LowerFormalArguments_32SVR4()
3494 case MVT::v4f32: in LowerFormalArguments_32SVR4()
3497 case MVT::v2f64: in LowerFormalArguments_32SVR4()
3498 case MVT::v2i64: in LowerFormalArguments_32SVR4()
3501 case MVT::v4f64: in LowerFormalArguments_32SVR4()
3504 case MVT::v4i1: in LowerFormalArguments_32SVR4()
3512 ValVT == MVT::i1 ? MVT::i32 : ValVT); in LowerFormalArguments_32SVR4()
3514 if (ValVT == MVT::i1) in LowerFormalArguments_32SVR4()
3515 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue); in LowerFormalArguments_32SVR4()
3587 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8; in LowerFormalArguments_32SVR4()
3624 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); in LowerFormalArguments_32SVR4()
3629 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl, in LowerFormalArguments_32SVR4()
3636 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_32SVR4()
3648 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
3651 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
3813 EVT ObjType = (ObjSize == 1 ? MVT::i8 : in LowerFormalArguments_64SVR4()
3814 (ObjSize == 2 ? MVT::i16 : MVT::i32)); in LowerFormalArguments_64SVR4()
3861 case MVT::i1: in LowerFormalArguments_64SVR4()
3862 case MVT::i32: in LowerFormalArguments_64SVR4()
3863 case MVT::i64: in LowerFormalArguments_64SVR4()
3867 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
3869 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
3881 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
3883 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
3898 case MVT::f32: in LowerFormalArguments_64SVR4()
3899 case MVT::f64: in LowerFormalArguments_64SVR4()
3906 if (ObjectVT == MVT::f32) in LowerFormalArguments_64SVR4()
3927 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
3929 if (ObjectVT == MVT::f32) { in LowerFormalArguments_64SVR4()
3931 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal, in LowerFormalArguments_64SVR4()
3932 DAG.getConstant(32, dl, MVT::i32)); in LowerFormalArguments_64SVR4()
3933 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); in LowerFormalArguments_64SVR4()
3954 case MVT::v4f32: in LowerFormalArguments_64SVR4()
3955 case MVT::v4i32: in LowerFormalArguments_64SVR4()
3956 case MVT::v8i16: in LowerFormalArguments_64SVR4()
3957 case MVT::v16i8: in LowerFormalArguments_64SVR4()
3958 case MVT::v2f64: in LowerFormalArguments_64SVR4()
3959 case MVT::v2i64: in LowerFormalArguments_64SVR4()
3960 case MVT::v1i128: in LowerFormalArguments_64SVR4()
3961 case MVT::f128: in LowerFormalArguments_64SVR4()
3980 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && in LowerFormalArguments_64SVR4()
3984 case MVT::v4f64: in LowerFormalArguments_64SVR4()
3985 case MVT::v4i1: in LowerFormalArguments_64SVR4()
3988 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32; in LowerFormalArguments_64SVR4()
3992 case MVT::v4f64: RC = &PPC::QFRCRegClass; break; in LowerFormalArguments_64SVR4()
3993 case MVT::v4f32: RC = &PPC::QSRCRegClass; break; in LowerFormalArguments_64SVR4()
4064 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_64SVR4()
4080 bool isPPC64 = PtrVT == MVT::i64; in LowerFormalArguments_Darwin()
4136 case MVT::i1: in LowerFormalArguments_Darwin()
4137 case MVT::i32: in LowerFormalArguments_Darwin()
4138 case MVT::f32: in LowerFormalArguments_Darwin()
4141 case MVT::i64: // PPC64 in LowerFormalArguments_Darwin()
4142 case MVT::f64: in LowerFormalArguments_Darwin()
4147 case MVT::v4f32: in LowerFormalArguments_Darwin()
4148 case MVT::v4i32: in LowerFormalArguments_Darwin()
4149 case MVT::v8i16: in LowerFormalArguments_Darwin()
4150 case MVT::v16i8: in LowerFormalArguments_Darwin()
4183 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || in LowerFormalArguments_Darwin()
4184 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { in LowerFormalArguments_Darwin()
4222 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16; in LowerFormalArguments_Darwin()
4262 case MVT::i1: in LowerFormalArguments_Darwin()
4263 case MVT::i32: in LowerFormalArguments_Darwin()
4267 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments_Darwin()
4269 if (ObjectVT == MVT::i1) in LowerFormalArguments_Darwin()
4270 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal); in LowerFormalArguments_Darwin()
4282 case MVT::i64: // PPC64 in LowerFormalArguments_Darwin()
4285 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_Darwin()
4287 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_Darwin()
4301 case MVT::f32: in LowerFormalArguments_Darwin()
4302 case MVT::f64: in LowerFormalArguments_Darwin()
4313 if (ObjectVT == MVT::f32) in LowerFormalArguments_Darwin()
4327 case MVT::v4f32: in LowerFormalArguments_Darwin()
4328 case MVT::v4i32: in LowerFormalArguments_Darwin()
4329 case MVT::v8i16: in LowerFormalArguments_Darwin()
4330 case MVT::v16i8: in LowerFormalArguments_Darwin()
4424 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_Darwin()
4770 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
4799 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
4816 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
4841 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
4859 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerMemOpCallTo()
4861 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerMemOpCallTo()
4885 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2); in PrepareTailCall()
4922 NodeTys.push_back(MVT::Other); // Returns a chain in PrepareCall()
4923 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. in PrepareCall()
5019 if (LDChain.getValueType() == MVT::Glue) in PrepareCall()
5028 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI, in PrepareCall()
5033 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); in PrepareCall()
5035 DAG.getLoad(MVT::i64, dl, LDChain, AddPtr, MPI.getWithOffset(16), in PrepareCall()
5039 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff); in PrepareCall()
5041 DAG.getLoad(MVT::i64, dl, LDChain, AddTOC, MPI.getWithOffset(8), in PrepareCall()
5070 NodeTys.push_back(MVT::Other); in PrepareCall()
5071 NodeTys.push_back(MVT::Glue); in PrepareCall()
5090 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32)); in PrepareCall()
5176 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); in FinishCall()
5205 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops); in FinishCall()
5236 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff); in FinishCall()
5382 MVT ArgVT = Outs[i].VT; in LowerCall_32SVR4()
5439 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_32SVR4()
5494 if (Arg.getValueType() == MVT::i1) in LowerCall_32SVR4()
5496 dl, MVT::i32, Arg); in LowerCall_32SVR4()
5523 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32SVR4()
5537 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_32SVR4()
5676 case MVT::i1: in LowerCall_64SVR4()
5677 case MVT::i32: in LowerCall_64SVR4()
5678 case MVT::i64: in LowerCall_64SVR4()
5682 case MVT::v4i32: in LowerCall_64SVR4()
5683 case MVT::v8i16: in LowerCall_64SVR4()
5684 case MVT::v16i8: in LowerCall_64SVR4()
5685 case MVT::v2f64: in LowerCall_64SVR4()
5686 case MVT::v2i64: in LowerCall_64SVR4()
5687 case MVT::v1i128: in LowerCall_64SVR4()
5688 case MVT::f128: in LowerCall_64SVR4()
5692 case MVT::v4f32: in LowerCall_64SVR4()
5703 case MVT::f32: in LowerCall_64SVR4()
5704 case MVT::f64: in LowerCall_64SVR4()
5705 case MVT::v4f64: // QPX in LowerCall_64SVR4()
5706 case MVT::v4i1: // QPX in LowerCall_64SVR4()
5771 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_64SVR4()
5816 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) { in LowerCall_64SVR4()
5819 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
5843 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); in LowerCall_64SVR4()
5937 case MVT::i1: in LowerCall_64SVR4()
5938 case MVT::i32: in LowerCall_64SVR4()
5939 case MVT::i64: in LowerCall_64SVR4()
5967 case MVT::f32: in LowerCall_64SVR4()
5968 case MVT::f64: { in LowerCall_64SVR4()
5998 if (Arg.getValueType() != MVT::f32) { in LowerCall_64SVR4()
5999 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); in LowerCall_64SVR4()
6003 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6004 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
6010 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]); in LowerCall_64SVR4()
6011 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6014 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
6018 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6019 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
6021 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal, in LowerCall_64SVR4()
6022 DAG.getConstant(32, dl, MVT::i32)); in LowerCall_64SVR4()
6037 if (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
6055 ArgOffset += (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
6062 case MVT::v4f32: in LowerCall_64SVR4()
6063 case MVT::v4i32: in LowerCall_64SVR4()
6064 case MVT::v8i16: in LowerCall_64SVR4()
6065 case MVT::v16i8: in LowerCall_64SVR4()
6066 case MVT::v2f64: in LowerCall_64SVR4()
6067 case MVT::v2i64: in LowerCall_64SVR4()
6068 case MVT::v1i128: in LowerCall_64SVR4()
6069 case MVT::f128: in LowerCall_64SVR4()
6089 DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo()); in LowerCall_64SVR4()
6128 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 && in LowerCall_64SVR4()
6132 case MVT::v4f64: in LowerCall_64SVR4()
6133 case MVT::v4i1: { in LowerCall_64SVR4()
6134 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32; in LowerCall_64SVR4()
6144 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl, Store, in LowerCall_64SVR4()
6191 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_64SVR4()
6201 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); in LowerCall_64SVR4()
6245 bool isPPC64 = PtrVT == MVT::i64; in LowerCall_Darwin()
6276 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in LowerCall_Darwin()
6277 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in LowerCall_Darwin()
6278 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) { in LowerCall_Darwin()
6333 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_Darwin()
6335 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_Darwin()
6379 if (isPPC64 && Arg.getValueType() == MVT::i32) { in LowerCall_Darwin()
6382 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
6393 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; in LowerCall_Darwin()
6441 case MVT::i1: in LowerCall_Darwin()
6442 case MVT::i32: in LowerCall_Darwin()
6443 case MVT::i64: in LowerCall_Darwin()
6445 if (Arg.getValueType() == MVT::i1) in LowerCall_Darwin()
6456 case MVT::f32: in LowerCall_Darwin()
6457 case MVT::f64: in LowerCall_Darwin()
6473 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ in LowerCall_Darwin()
6487 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && in LowerCall_Darwin()
6498 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; in LowerCall_Darwin()
6500 case MVT::v4f32: in LowerCall_Darwin()
6501 case MVT::v4i32: in LowerCall_Darwin()
6502 case MVT::v8i16: in LowerCall_Darwin()
6503 case MVT::v16i8: in LowerCall_Darwin()
6524 DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo()); in LowerCall_Darwin()
6570 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || in LowerCall_Darwin()
6571 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { in LowerCall_Darwin()
6585 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_Darwin()
6679 RetOps.push_back(DAG.getRegister(*I, MVT::i64)); in LowerReturn()
6681 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64))); in LowerReturn()
6683 RetOps.push_back(DAG.getRegister(*I, MVT::i1)); in LowerReturn()
6685 RetOps.push_back(DAG.getRegister(*I, MVT::Other)); in LowerReturn()
6697 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
6806 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); in LowerDYNAMIC_STACKALLOC()
6825 DAG.getVTList(MVT::i32, MVT::Other), in lowerEH_SJLJ_SETJMP()
6832 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, in lowerEH_SJLJ_LONGJMP()
6840 assert(Op.getValueType() == MVT::i1 && in LowerLOAD()
6854 BasePtr, MVT::i8, MMO); in LowerLOAD()
6855 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD); in LowerLOAD()
6865 assert(Op.getOperand(1).getValueType() == MVT::i1 && in LowerSTORE()
6880 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO); in LowerSTORE()
6885 assert(Op.getValueType() == MVT::i1 && in LowerTRUNCATE()
6889 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1, in LowerTRUNCATE()
6930 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6931 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6933 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6934 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6936 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
6943 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6944 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6952 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6953 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6955 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); in LowerSELECT_CC()
6966 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6967 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6969 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6970 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6972 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
6976 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6977 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6982 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6983 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6988 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6989 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6994 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6995 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
7006 if (Src.getValueType() == MVT::f32) in LowerFP_TO_INTForReuse()
7007 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
7012 case MVT::i32: in LowerFP_TO_INTForReuse()
7017 dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
7019 case MVT::i64: in LowerFP_TO_INTForReuse()
7024 dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
7029 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
7031 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64); in LowerFP_TO_INTForReuse()
7044 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO); in LowerFP_TO_INTForReuse()
7050 if (Op.getValueType() == MVT::i32 && !i32Stack) { in LowerFP_TO_INTForReuse()
7070 if (Src.getValueType() == MVT::f32) in LowerFP_TO_INTDirectMove()
7071 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
7076 case MVT::i32: in LowerFP_TO_INTDirectMove()
7081 dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
7082 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
7084 case MVT::i64: in LowerFP_TO_INTDirectMove()
7089 dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
7090 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
7100 if (EnableQuadPrecision && (Op->getOperand(0).getValueType() == MVT::f128)) in LowerFP_TO_INT()
7105 if (Op.getOperand(0).getValueType() == MVT::ppcf128) { in LowerFP_TO_INT()
7106 if (Op.getValueType() == MVT::i32) { in LowerFP_TO_INT()
7109 MVT::f64, Op.getOperand(0), in LowerFP_TO_INT()
7112 MVT::f64, Op.getOperand(0), in LowerFP_TO_INT()
7116 SDValue Res = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi); in LowerFP_TO_INT()
7119 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in LowerFP_TO_INT()
7124 SDValue Tmp = DAG.getConstantFP(APF, dl, MVT::ppcf128); in LowerFP_TO_INT()
7128 SDValue True = DAG.getNode(ISD::FSUB, dl, MVT::ppcf128, in LowerFP_TO_INT()
7130 True = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, True); in LowerFP_TO_INT()
7131 True = DAG.getNode(ISD::ADD, dl, MVT::i32, True, in LowerFP_TO_INT()
7132 DAG.getConstant(0x80000000, dl, MVT::i32)); in LowerFP_TO_INT()
7133 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, in LowerFP_TO_INT()
7215 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in spliceIntoChain()
7216 NewResChain, DAG.getUNDEF(MVT::Other)); in spliceIntoChain()
7260 assert((Op.getValueType() == MVT::f32 || in LowerINT_TO_FPDirectMove()
7261 Op.getValueType() == MVT::f64) && in LowerINT_TO_FPDirectMove()
7267 bool SinglePrec = Op.getValueType() == MVT::f32; in LowerINT_TO_FPDirectMove()
7268 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32; in LowerINT_TO_FPDirectMove()
7275 dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
7276 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP); in LowerINT_TO_FPDirectMove()
7279 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
7280 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP); in LowerINT_TO_FPDirectMove()
7312 assert((Op.getValueType() == MVT::v2f64 || Op.getValueType() == MVT::v4f32) && in LowerINT_TO_FPVector()
7316 bool FourEltRes = Op.getValueType() == MVT::v4f32; in LowerINT_TO_FPVector()
7321 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector()
7364 if (EnableQuadPrecision && (Op.getValueType() == MVT::f128)) in LowerINT_TO_FP()
7367 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) { in LowerINT_TO_FP()
7368 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64) in LowerINT_TO_FP()
7375 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerINT_TO_FP()
7377 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64); in LowerINT_TO_FP()
7379 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerINT_TO_FP()
7381 if (Op.getValueType() != MVT::v4f64) in LowerINT_TO_FP()
7389 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in LowerINT_TO_FP()
7392 if (Op.getOperand(0).getValueType() == MVT::i1) in LowerINT_TO_FP()
7408 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in LowerINT_TO_FP()
7413 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in LowerINT_TO_FP()
7414 ? MVT::f32 in LowerINT_TO_FP()
7415 : MVT::f64; in LowerINT_TO_FP()
7417 if (Op.getOperand(0).getValueType() == MVT::i64) { in LowerINT_TO_FP()
7429 if (Op.getValueType() == MVT::f32 && in LowerINT_TO_FP()
7439 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
7440 SINT, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
7441 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
7442 Round, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
7443 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); in LowerINT_TO_FP()
7444 Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
7445 Round, DAG.getConstant(-2048, dl, MVT::i64)); in LowerINT_TO_FP()
7455 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, in LowerINT_TO_FP()
7456 SINT, DAG.getConstant(53, dl, MVT::i32)); in LowerINT_TO_FP()
7457 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
7458 Cond, DAG.getConstant(1, dl, MVT::i64)); in LowerINT_TO_FP()
7459 Cond = DAG.getSetCC(dl, MVT::i32, in LowerINT_TO_FP()
7460 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT); in LowerINT_TO_FP()
7462 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); in LowerINT_TO_FP()
7469 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) { in LowerINT_TO_FP()
7470 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, in LowerINT_TO_FP()
7474 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) { in LowerINT_TO_FP()
7480 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
7481 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
7484 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
7490 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
7491 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
7497 SINT.getOperand(0).getValueType() == MVT::i32) { in LowerINT_TO_FP()
7509 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
7524 dl, DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
7525 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
7527 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); in LowerINT_TO_FP()
7531 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) in LowerINT_TO_FP()
7533 MVT::f32, FP, DAG.getIntPtrConstant(0, dl)); in LowerINT_TO_FP()
7537 assert(Op.getOperand(0).getValueType() == MVT::i32 && in LowerINT_TO_FP()
7551 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI, in LowerINT_TO_FP()
7561 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
7577 dl, DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
7578 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
7588 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, in LowerINT_TO_FP()
7598 MVT::f64, dl, Store, FIdx, in LowerINT_TO_FP()
7604 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) in LowerINT_TO_FP()
7605 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
7638 MVT::f64, // return register in LowerFLT_ROUNDS_()
7639 MVT::Glue // unused in this context in LowerFLT_ROUNDS_()
7652 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo()); in LowerFLT_ROUNDS_()
7656 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFLT_ROUNDS_()
7657 CWD, DAG.getConstant(3, dl, MVT::i32)); in LowerFLT_ROUNDS_()
7659 DAG.getNode(ISD::SRL, dl, MVT::i32, in LowerFLT_ROUNDS_()
7660 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFLT_ROUNDS_()
7661 DAG.getNode(ISD::XOR, dl, MVT::i32, in LowerFLT_ROUNDS_()
7662 CWD, DAG.getConstant(3, dl, MVT::i32)), in LowerFLT_ROUNDS_()
7663 DAG.getConstant(3, dl, MVT::i32)), in LowerFLT_ROUNDS_()
7664 DAG.getConstant(1, dl, MVT::i32)); in LowerFLT_ROUNDS_()
7667 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); in LowerFLT_ROUNDS_()
7770 static const MVT VTys[] = { // canonical VT to use for each size. in BuildSplatI()
7771 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 in BuildSplatI()
7774 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; in BuildSplatI()
7789 const SDLoc &dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
7790 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
7792 DAG.getConstant(IID, dl, MVT::i32), Op); in BuildIntrinsicOp()
7799 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
7800 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
7802 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS); in BuildIntrinsicOp()
7809 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
7810 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
7812 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2); in BuildIntrinsicOp()
7820 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); in BuildVSLDOI()
7821 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); in BuildVSLDOI()
7826 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); in BuildVSLDOI()
7846 bool RightType = VecVT == MVT::v2f64 || in haveEfficientBuildVectorPattern()
7847 (HasP8Vector && VecVT == MVT::v4f32) || in haveEfficientBuildVectorPattern()
7848 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32)); in haveEfficientBuildVectorPattern()
7890 (Op.getValueType() != MVT::f128 ) || in LowerBITCAST()
7892 (Op0.getOperand(0).getValueType() != MVT::i64) || in LowerBITCAST()
7893 (Op0.getOperand(1).getValueType() != MVT::i64)) in LowerBITCAST()
7896 return DAG.getNode(PPCISD::BUILD_FP128, dl, MVT::f128, Op0.getOperand(0), in LowerBITCAST()
7911 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) { in LowerBUILD_VECTOR()
7955 SDVTList VTs = DAG.getVTList({MVT::v4i1, /*chain*/ MVT::Other}); in LowerBUILD_VECTOR()
7957 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32, in LowerBUILD_VECTOR()
7973 PtrInfo.getWithOffset(Offset), MVT::i32)); in LowerBUILD_VECTOR()
7977 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue); in LowerBUILD_VECTOR()
7986 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerBUILD_VECTOR()
7996 DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32), in LowerBUILD_VECTOR()
7998 SDVTList VTs = DAG.getVTList({MVT::v4f64, /*chain*/ MVT::Other}); in LowerBUILD_VECTOR()
8001 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerBUILD_VECTOR()
8002 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerBUILD_VECTOR()
8003 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32), in LowerBUILD_VECTOR()
8006 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::v4f64); in LowerBUILD_VECTOR()
8008 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ); in LowerBUILD_VECTOR()
8041 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { in LowerBUILD_VECTOR()
8042 SDValue Z = DAG.getConstant(0, dl, MVT::v4i32); in LowerBUILD_VECTOR()
8055 dl, MVT::i32)); in LowerBUILD_VECTOR()
8056 SDValue NewBV = DAG.getBuildVector(MVT::v16i8, dl, Ops); in LowerBUILD_VECTOR()
8057 if (Op.getValueType() != MVT::v16i8) in LowerBUILD_VECTOR()
8066 if (Op.getValueType() != MVT::v16i8) in LowerBUILD_VECTOR()
8068 DAG.getConstant(SplatBits, dl, MVT::v16i8)); in LowerBUILD_VECTOR()
8092 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32); in LowerBUILD_VECTOR()
8093 EVT VT = (SplatSize == 1 ? MVT::v16i8 : in LowerBUILD_VECTOR()
8094 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); in LowerBUILD_VECTOR()
8095 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32); in LowerBUILD_VECTOR()
8108 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); in LowerBUILD_VECTOR()
8115 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); in LowerBUILD_VECTOR()
8136 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
8147 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
8158 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
8170 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
8181 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
8187 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
8193 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
8273 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); in GeneratePerfectShuffle()
8274 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); in GeneratePerfectShuffle()
8275 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); in GeneratePerfectShuffle()
8371 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2, in lowerToVINSERTB()
8372 DAG.getConstant(ShiftElts, dl, MVT::i32)); in lowerToVINSERTB()
8373 return DAG.getNode(PPCISD::VECINSERT, dl, MVT::v16i8, V1, Shl, in lowerToVINSERTB()
8374 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTB()
8376 return DAG.getNode(PPCISD::VECINSERT, dl, MVT::v16i8, V1, V2, in lowerToVINSERTB()
8377 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTB()
8476 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); in lowerToVINSERTH()
8479 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2, in lowerToVINSERTH()
8480 DAG.getConstant(2 * ShiftElts, dl, MVT::i32)); in lowerToVINSERTH()
8481 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, Shl); in lowerToVINSERTH()
8482 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2, in lowerToVINSERTH()
8483 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTH()
8484 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in lowerToVINSERTH()
8486 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); in lowerToVINSERTH()
8487 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2, in lowerToVINSERTH()
8488 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTH()
8489 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in lowerToVINSERTH()
8512 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
8513 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2); in LowerVECTOR_SHUFFLE()
8515 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv2, Conv2, in LowerVECTOR_SHUFFLE()
8516 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8517 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Shl, in LowerVECTOR_SHUFFLE()
8518 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8519 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in LowerVECTOR_SHUFFLE()
8521 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
8522 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8523 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in LowerVECTOR_SHUFFLE()
8539 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
8541 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2.isUndef() ? V1 : V2); in LowerVECTOR_SHUFFLE()
8543 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
8544 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8545 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Shl); in LowerVECTOR_SHUFFLE()
8552 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1); in LowerVECTOR_SHUFFLE()
8554 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2.isUndef() ? V1 : V2); in LowerVECTOR_SHUFFLE()
8556 SDValue PermDI = DAG.getNode(PPCISD::XXPERMDI, dl, MVT::v2i64, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
8557 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8558 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, PermDI); in LowerVECTOR_SHUFFLE()
8563 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); in LowerVECTOR_SHUFFLE()
8564 SDValue ReveHWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v8i16, Conv); in LowerVECTOR_SHUFFLE()
8565 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveHWord); in LowerVECTOR_SHUFFLE()
8567 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
8568 SDValue ReveWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v4i32, Conv); in LowerVECTOR_SHUFFLE()
8569 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveWord); in LowerVECTOR_SHUFFLE()
8571 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1); in LowerVECTOR_SHUFFLE()
8572 SDValue ReveDWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v2i64, Conv); in LowerVECTOR_SHUFFLE()
8573 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveDWord); in LowerVECTOR_SHUFFLE()
8575 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, V1); in LowerVECTOR_SHUFFLE()
8576 SDValue ReveQWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v1i128, Conv); in LowerVECTOR_SHUFFLE()
8577 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveQWord); in LowerVECTOR_SHUFFLE()
8585 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
8586 SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv, in LowerVECTOR_SHUFFLE()
8587 DAG.getConstant(SplatIdx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8588 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Splat); in LowerVECTOR_SHUFFLE()
8593 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); in LowerVECTOR_SHUFFLE()
8594 SDValue Swap = DAG.getNode(PPCISD::SWAP_NO_CHAIN, dl, MVT::v2f64, Conv); in LowerVECTOR_SHUFFLE()
8595 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Swap); in LowerVECTOR_SHUFFLE()
8608 DAG.getConstant(AlignIdx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8617 DAG.getConstant(SplatIdx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8630 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64, in LowerVECTOR_SHUFFLE()
8631 DAG.getConstant(idx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8755 dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
8758 MVT::i32)); in LowerVECTOR_SHUFFLE()
8761 SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask); in LowerVECTOR_SHUFFLE()
9029 return DAG.getRegister(PPC::X13, MVT::i64); in LowerINTRINSIC_WO_CHAIN()
9030 return DAG.getRegister(PPC::R2, MVT::i32); in LowerINTRINSIC_WO_CHAIN()
9044 DAG.getConstant(CompareOpc, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
9052 DAG.getConstant(CompareOpc, dl, MVT::i32) in LowerINTRINSIC_WO_CHAIN()
9054 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue }; in LowerINTRINSIC_WO_CHAIN()
9059 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
9060 DAG.getRegister(PPC::CR6, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
9083 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
9084 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
9086 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
9087 DAG.getConstant(1, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
9091 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
9092 DAG.getConstant(1, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
9106 return SDValue(DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other, in LowerINTRINSIC_VOID()
9107 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, in LowerINTRINSIC_VOID()
9134 Op = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, Op.getOperand(0), in LowerBSWAP()
9137 Op = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v2i64, Op); in LowerBSWAP()
9142 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Op, in LowerBSWAP()
9143 DAG.getTargetConstant(VectorIndex, dl, MVT::i32)); in LowerBSWAP()
9168 DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp, in LowerATOMIC_CMP_SWAP()
9169 DAG.getConstant(MaskVal, dl, MVT::i32)); in LowerATOMIC_CMP_SWAP()
9177 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::Other); in LowerATOMIC_CMP_SWAP()
9179 (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16; in LowerATOMIC_CMP_SWAP()
9214 if (VT == MVT::v8i16 || VT == MVT::v16i8) { in LowerINSERT_VECTOR_ELT()
9223 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerINSERT_VECTOR_ELT()
9233 assert(N->getOperand(0).getValueType() == MVT::v4i1 && in LowerEXTRACT_VECTOR_ELT()
9244 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerEXTRACT_VECTOR_ELT()
9248 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64); in LowerEXTRACT_VECTOR_ELT()
9250 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerEXTRACT_VECTOR_ELT()
9253 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerEXTRACT_VECTOR_ELT()
9254 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32), in LowerEXTRACT_VECTOR_ELT()
9266 DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32), in LowerEXTRACT_VECTOR_ELT()
9268 SDVTList VTs = DAG.getVTList(/*chain*/ MVT::Other); in LowerEXTRACT_VECTOR_ELT()
9271 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerEXTRACT_VECTOR_ELT()
9279 DAG.getLoad(MVT::i32, dl, StoreChain, Idx, PtrInfo.getWithOffset(Offset)); in LowerEXTRACT_VECTOR_ELT()
9284 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal); in LowerEXTRACT_VECTOR_ELT()
9295 if (Op.getValueType() == MVT::v4f64 || in LowerVectorLoad()
9296 Op.getValueType() == MVT::v4f32) { in LowerVectorLoad()
9338 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in LowerVectorLoad()
9350 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower"); in LowerVectorLoad()
9362 ISD::EXTLOAD, dl, MVT::i32, LoadChain, Idx, in LowerVectorLoad()
9363 LN->getPointerInfo().getWithOffset(i), MVT::i8, in LowerVectorLoad()
9368 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains); in LowerVectorLoad()
9369 SDValue Value = DAG.getBuildVector(MVT::v4i1, dl, VectElmts); in LowerVectorLoad()
9384 if (Value.getValueType() == MVT::v4f64 || in LowerVectorStore()
9385 Value.getValueType() == MVT::v4f32) { in LowerVectorStore()
9428 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerVectorStore()
9439 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower"); in LowerVectorStore()
9444 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerVectorStore()
9448 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64); in LowerVectorStore()
9450 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerVectorStore()
9453 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerVectorStore()
9454 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32), in LowerVectorStore()
9465 DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32), in LowerVectorStore()
9467 SDVTList VTs = DAG.getVTList(/*chain*/ MVT::Other); in LowerVectorStore()
9470 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerVectorStore()
9479 Loads[i] = DAG.getLoad(MVT::i32, dl, StoreChain, Idx, in LowerVectorStore()
9484 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in LowerVectorStore()
9493 MVT::i8, /* Alignment = */ 1, SN->getMemOperand()->getFlags(), in LowerVectorStore()
9497 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerVectorStore()
9504 if (Op.getValueType() == MVT::v4i32) { in LowerMUL()
9507 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); in LowerMUL()
9508 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. in LowerMUL()
9514 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); in LowerMUL()
9515 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); in LowerMUL()
9516 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); in LowerMUL()
9521 LHS, RHS, DAG, dl, MVT::v4i32); in LowerMUL()
9524 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); in LowerMUL()
9528 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); in LowerMUL()
9529 } else if (Op.getValueType() == MVT::v8i16) { in LowerMUL()
9532 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); in LowerMUL()
9536 } else if (Op.getValueType() == MVT::v16i8) { in LowerMUL()
9542 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
9543 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); in LowerMUL()
9547 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
9548 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); in LowerMUL()
9565 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops); in LowerMUL()
9567 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); in LowerMUL()
9580 assert((VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || in LowerABS()
9581 VT == MVT::v16i8) && in LowerABS()
9583 assert((VT != MVT::v2i64 || Subtarget.hasP8Altivec()) && in LowerABS()
9601 if (VT == MVT::v2i64) in LowerABS()
9603 else if (VT == MVT::v8i16) in LowerABS()
9605 else if (VT == MVT::v16i8) in LowerABS()
9694 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); in ReplaceNodeResults()
9707 assert(N->getValueType(0) == MVT::i1 && in ReplaceNodeResults()
9711 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
9715 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewInt)); in ReplaceNodeResults()
9725 if (VT == MVT::i64) { in ReplaceNodeResults()
9736 if (N->getOperand(0).getValueType() == MVT::ppcf128) in ReplaceNodeResults()
10114 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
10118 MVT PVT = getPointerTy(MF->getDataLayout()); in emitEHSjLjSetJmp()
10119 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjSetJmp()
10250 MVT PVT = getPointerTy(MF->getDataLayout()); in emitEHSjLjLongJmp()
10251 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjLongJmp()
10255 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in emitEHSjLjLongJmp()
10258 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; in emitEHSjLjLongJmp()
10259 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; in emitEHSjLjLongJmp()
10261 (PVT == MVT::i64) in emitEHSjLjLongJmp()
10278 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
10290 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
10302 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
10314 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
10326 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
10336 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); in emitEHSjLjLongJmp()
10337 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); in emitEHSjLjLongJmp()
10990 if (VT.getScalarType() == MVT::f64) in getEstimateRefinementSteps()
11000 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getSqrtEstimate()
11001 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getSqrtEstimate()
11002 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getSqrtEstimate()
11003 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getSqrtEstimate()
11004 (VT == MVT::v4f32 && Subtarget.hasQPX()) || in getSqrtEstimate()
11005 (VT == MVT::v4f64 && Subtarget.hasQPX())) { in getSqrtEstimate()
11019 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
11020 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
11021 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
11022 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRecipEstimate()
11023 (VT == MVT::v4f32 && Subtarget.hasQPX()) || in getRecipEstimate()
11024 (VT == MVT::v4f64 && Subtarget.hasQPX())) { in getRecipEstimate()
11124 VT = MVT::v4f64; in isConsecutiveLS()
11128 VT = MVT::v4f32; in isConsecutiveLS()
11132 VT = MVT::v2f64; in isConsecutiveLS()
11136 VT = MVT::v2f32; in isConsecutiveLS()
11144 VT = MVT::v4i32; in isConsecutiveLS()
11148 VT = MVT::v2f64; in isConsecutiveLS()
11151 VT = MVT::i8; in isConsecutiveLS()
11154 VT = MVT::i16; in isConsecutiveLS()
11157 VT = MVT::i32; in isConsecutiveLS()
11170 VT = MVT::v4f64; in isConsecutiveLS()
11174 VT = MVT::v4f32; in isConsecutiveLS()
11178 VT = MVT::v2f64; in isConsecutiveLS()
11182 VT = MVT::v2f32; in isConsecutiveLS()
11189 VT = MVT::v4i32; in isConsecutiveLS()
11192 VT = MVT::v2f64; in isConsecutiveLS()
11195 VT = MVT::v4i32; in isConsecutiveLS()
11198 VT = MVT::v2f64; in isConsecutiveLS()
11201 VT = MVT::i8; in isConsecutiveLS()
11204 VT = MVT::i16; in isConsecutiveLS()
11207 VT = MVT::i32; in isConsecutiveLS()
11295 auto Op0 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(0), in generateEquivalentSub()
11296 DAG.getConstant(Size, DL, MVT::i32)); in generateEquivalentSub()
11297 auto Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1), in generateEquivalentSub()
11298 DAG.getConstant(Size, DL, MVT::i32)); in generateEquivalentSub()
11305 auto SubNode = DAG.getNode(ISD::SUB, DL, MVT::i64, Op0, Op1); in generateEquivalentSub()
11309 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, in generateEquivalentSub()
11310 DAG.getConstant(Size - 1, DL, MVT::i32)); in generateEquivalentSub()
11315 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted, in generateEquivalentSub()
11316 DAG.getConstant(1, DL, MVT::i64)); in generateEquivalentSub()
11318 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Final); in generateEquivalentSub()
11379 N->getValueType(0) != MVT::i1) in DAGCombineTruncBoolExt()
11382 if (N->getOperand(0).getValueType() != MVT::i32 && in DAGCombineTruncBoolExt()
11383 N->getOperand(0).getValueType() != MVT::i64) in DAGCombineTruncBoolExt()
11456 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
11487 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
11590 PromOp.getOperand(0).getValueType() != MVT::i1) { in DAGCombineTruncBoolExt()
11598 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue); in DAGCombineTruncBoolExt()
11612 PromOp.getOperand(C).getValueType() != MVT::i1) || in DAGCombineTruncBoolExt()
11614 PromOp.getOperand(C+1).getValueType() != MVT::i1)) { in DAGCombineTruncBoolExt()
11629 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]); in DAGCombineTruncBoolExt()
11632 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops)); in DAGCombineTruncBoolExt()
11663 if (N->getValueType(0) != MVT::i32 && in DAGCombineExtBoolTrunc()
11664 N->getValueType(0) != MVT::i64) in DAGCombineExtBoolTrunc()
11667 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
11668 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
11962 Op.getValueType() == MVT::f64; in isFPExtLoad()
12032 MVT::f32, In.getOperand(0), in combineElementTruncationToVectorTruncation()
12047 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32; in combineElementTruncationToVectorTruncation()
12311 if (N->getValueType(0) != MVT::v2f64) in DAGCombineBuildVector()
12335 if (Ext1.getValueType() != MVT::i32 || in DAGCombineBuildVector()
12336 Ext2.getValueType() != MVT::i32) in DAGCombineBuildVector()
12353 return DAG.getNode(NodeType, dl, MVT::v2f64, in DAGCombineBuildVector()
12372 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in combineFPToIntToFP()
12374 if (Op.getOperand(0).getValueType().getSimpleVT() <= MVT(MVT::i1) || in combineFPToIntToFP()
12375 Op.getOperand(0).getValueType().getSimpleVT() > MVT(MVT::i64)) in combineFPToIntToFP()
12380 (FirstOperand.getValueType() == MVT::i8 || in combineFPToIntToFP()
12381 FirstOperand.getValueType() == MVT::i16); in combineFPToIntToFP()
12384 bool DstDouble = Op.getValueType() == MVT::f64; in combineFPToIntToFP()
12389 DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2, in combineFPToIntToFP()
12394 DAG.getVTList(MVT::f64, MVT::Other), in combineFPToIntToFP()
12395 Ops, MVT::i8, LDN->getMemOperand()); in combineFPToIntToFP()
12400 SDValue Ext = DAG.getNode(PPCISD::VEXTS, dl, MVT::f64, ExtOps); in combineFPToIntToFP()
12401 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ext); in combineFPToIntToFP()
12403 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld); in combineFPToIntToFP()
12411 if (Op.getOperand(0).getValueType() == MVT::i32) in combineFPToIntToFP()
12419 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
12424 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
12425 ? MVT::f32 in combineFPToIntToFP()
12426 : MVT::f64; in combineFPToIntToFP()
12434 if (Src.getValueType() == MVT::f32) { in combineFPToIntToFP()
12435 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in combineFPToIntToFP()
12437 } else if (Src.getValueType() != MVT::f64) { in combineFPToIntToFP()
12446 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src); in combineFPToIntToFP()
12449 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
12451 MVT::f32, FP, DAG.getIntPtrConstant(0, dl)); in combineFPToIntToFP()
12497 MVT VecTy = N->getValueType(0).getSimpleVT(); in expandVSXLoadForLE()
12508 DAG.getVTList(MVT::v2f64, MVT::Other), in expandVSXLoadForLE()
12509 LoadOps, MVT::v2f64, MMO); in expandVSXLoadForLE()
12514 PPCISD::XXSWAPD, dl, DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Load); in expandVSXLoadForLE()
12518 if (VecTy != MVT::v2f64) { in expandVSXLoadForLE()
12522 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other), in expandVSXLoadForLE()
12568 MVT VecTy = Src.getValueType().getSimpleVT(); in expandVSXStoreForLE()
12578 if (VecTy != MVT::v2f64) { in expandVSXStoreForLE()
12579 Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src); in expandVSXStoreForLE()
12584 DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src); in expandVSXStoreForLE()
12589 DAG.getVTList(MVT::Other), in expandVSXStoreForLE()
12616 (Op1VT == MVT::i32 || Op1VT == MVT::i64 || in combineStoreFPToInt()
12617 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
12619 if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() || in combineStoreFPToInt()
12625 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); in combineStoreFPToInt()
12635 dl, ResVT == MVT::f128 ? MVT::f128 : MVT::f64, Val); in combineStoreFPToInt()
12645 DAG.getVTList(MVT::Other), Ops, in combineStoreFPToInt()
12711 (Op1VT == MVT::i32 || Op1VT == MVT::i16 || in PerformDAGCombine()
12712 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
12722 if (BSwapOp.getValueType() == MVT::i16) in PerformDAGCombine()
12723 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); in PerformDAGCombine()
12730 DAG.getConstant(Shift, dl, MVT::i32)); in PerformDAGCombine()
12732 if (Op1VT == MVT::i64) in PerformDAGCombine()
12733 BSwapOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BSwapOp); in PerformDAGCombine()
12740 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), in PerformDAGCombine()
12748 isa<ConstantSDNode>(N->getOperand(1)) && Op1VT == MVT::i32) { in PerformDAGCombine()
12753 SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64); in PerformDAGCombine()
12767 MVT StoreVT = Op1VT.getSimpleVT(); in PerformDAGCombine()
12769 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 || in PerformDAGCombine()
12770 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32)) in PerformDAGCombine()
12782 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine()
12784 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
12785 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
12797 if (VT != MVT::i64) in PerformDAGCombine()
12824 Trunc->getValueType(0) != MVT::i32 || in PerformDAGCombine()
12835 Trunc2->getValueType(0) != MVT::i32 || in PerformDAGCombine()
12843 Bitcast->getValueType(0) != MVT::f32) in PerformDAGCombine()
12846 Bitcast2->getValueType(0) != MVT::f32) in PerformDAGCombine()
12866 SDValue FloatLoad = DAG.getLoad(MVT::f32, dl, LD->getChain(), BasePtr, in PerformDAGCombine()
12873 MVT::f32, dl, SDValue(FloatLoad.getNode(), 1), AddPtr, in PerformDAGCombine()
12902 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 || in PerformDAGCombine()
12903 VT == MVT::v4i32 || VT == MVT::v4f32)) || in PerformDAGCombine()
12904 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) && in PerformDAGCombine()
12937 MVT PermCntlTy, PermTy, LDTy; in PerformDAGCombine()
12943 PermCntlTy = MVT::v16i8; in PerformDAGCombine()
12944 PermTy = MVT::v4i32; in PerformDAGCombine()
12945 LDTy = MVT::v4i32; in PerformDAGCombine()
12947 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld : in PerformDAGCombine()
12949 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd : in PerformDAGCombine()
12952 PermCntlTy = MVT::v4f64; in PerformDAGCombine()
12953 PermTy = MVT::v4f64; in PerformDAGCombine()
12976 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
13006 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
13009 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in PerformDAGCombine()
13029 DAG.getTargetConstant(1, dl, MVT::i64)); in PerformDAGCombine()
13102 if ((V1.getSimpleValueType() == MVT::v4i32 || in PerformDAGCombine()
13103 V1.getSimpleValueType() == MVT::v8i16 || in PerformDAGCombine()
13104 V1.getSimpleValueType() == MVT::v16i8) && in PerformDAGCombine()
13159 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || in PerformDAGCombine()
13161 N->getValueType(0) == MVT::i64))) { in PerformDAGCombine()
13172 DAG.getVTList(N->getValueType(0) == MVT::i64 ? in PerformDAGCombine()
13173 MVT::i64 : MVT::i32, MVT::Other), in PerformDAGCombine()
13178 if (N->getValueType(0) == MVT::i16) in PerformDAGCombine()
13179 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); in PerformDAGCombine()
13257 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other, in PerformDAGCombine()
13297 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other, in PerformDAGCombine()
13316 return DAG.getNode(ISD::BR, dl, MVT::Other, in PerformDAGCombine()
13326 DAG.getConstant(CompareOpc, dl, MVT::i32) in PerformDAGCombine()
13328 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue }; in PerformDAGCombine()
13349 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), in PerformDAGCombine()
13350 DAG.getConstant(CompOpc, dl, MVT::i32), in PerformDAGCombine()
13351 DAG.getRegister(PPC::CR6, MVT::i32), in PerformDAGCombine()
13373 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
13375 if ((VT != MVT::i32 && VT != MVT::i64) || in BuildSDIVPow2()
13411 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) in computeKnownBitsForTargetNode()
13571 MVT VT) const { in getRegForInlineAsmConstraint()
13576 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
13580 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
13589 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
13591 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
13594 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
13596 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
13598 if (VT == MVT::v4f64 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
13600 if (VT == MVT::v4f32 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
13605 if (VT == MVT::v4f64 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
13607 if (VT == MVT::v4f32 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
13623 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
13638 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
13679 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative in LowerAsmOperandForConstraint()
13791 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
13813 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR()
13838 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) || in getRegisterByName()
13839 (!isPPC64 && VT != MVT::i32)) in getRegisterByName()
13842 bool is64Bit = isPPC64 && VT == MVT::i64; in getRegisterByName()
13911 VT = MVT::i8; in getTgtMemIntrinsic()
13914 VT = MVT::i16; in getTgtMemIntrinsic()
13917 VT = MVT::i32; in getTgtMemIntrinsic()
13920 VT = MVT::v2f64; in getTgtMemIntrinsic()
13923 VT = MVT::v4f64; in getTgtMemIntrinsic()
13926 VT = MVT::v4f32; in getTgtMemIntrinsic()
13929 VT = MVT::v2f64; in getTgtMemIntrinsic()
13932 VT = MVT::v2f32; in getTgtMemIntrinsic()
13935 VT = MVT::v4i32; in getTgtMemIntrinsic()
13957 VT = MVT::v4f64; in getTgtMemIntrinsic()
13960 VT = MVT::v4f32; in getTgtMemIntrinsic()
13963 VT = MVT::v2f64; in getTgtMemIntrinsic()
13966 VT = MVT::v2f32; in getTgtMemIntrinsic()
13969 VT = MVT::v4i32; in getTgtMemIntrinsic()
13997 VT = MVT::i8; in getTgtMemIntrinsic()
14000 VT = MVT::i16; in getTgtMemIntrinsic()
14003 VT = MVT::i32; in getTgtMemIntrinsic()
14006 VT = MVT::v2f64; in getTgtMemIntrinsic()
14009 VT = MVT::v4f64; in getTgtMemIntrinsic()
14012 VT = MVT::v4f32; in getTgtMemIntrinsic()
14015 VT = MVT::v2f64; in getTgtMemIntrinsic()
14018 VT = MVT::v2f32; in getTgtMemIntrinsic()
14021 VT = MVT::v4i32; in getTgtMemIntrinsic()
14042 VT = MVT::v4f64; in getTgtMemIntrinsic()
14045 VT = MVT::v4f32; in getTgtMemIntrinsic()
14048 VT = MVT::v2f64; in getTgtMemIntrinsic()
14051 VT = MVT::v2f32; in getTgtMemIntrinsic()
14054 VT = MVT::v4i32; in getTgtMemIntrinsic()
14097 return MVT::v4f64; in getOptimalMemOpType()
14105 return MVT::v4i32; in getOptimalMemOpType()
14109 return MVT::i64; in getOptimalMemOpType()
14112 return MVT::i32; in getOptimalMemOpType()
14146 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 || in isZExtFree()
14147 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
14165 if (DestVT == MVT::f128) in isFPExtFree()
14196 if (VT != MVT::v2f64 && VT != MVT::v2i64 && in allowsMisalignedMemoryAccesses()
14197 VT != MVT::v4f32 && VT != MVT::v4i32) in allowsMisalignedMemoryAccesses()
14204 if (VT == MVT::ppcf128) in allowsMisalignedMemoryAccesses()
14220 case MVT::f32: in isFMAFasterThanFMulAndFAdd()
14221 case MVT::f64: in isFMAFasterThanFMulAndFAdd()
14223 case MVT::f128: in isFMAFasterThanFMulAndFAdd()
14258 if (VT == MVT::v2i64) in shouldExpandBuildVectorWithShuffles()
14357 case MVT::f32: in isFPImmLegal()
14358 case MVT::f64: in isFPImmLegal()
14359 case MVT::ppcf128: in isFPImmLegal()
14406 N0.getOperand(0).getValueType() != MVT::i32 || in combineSHL()
14407 CN1 == nullptr || N->getValueType(0) != MVT::i64) in combineSHL()
14421 if (ShiftBy.getValueType() == MVT::i64) in combineSHL()
14422 ShiftBy = DCI.DAG.getConstant(CN1->getZExtValue(), DL, MVT::i32); in combineSHL()
14424 return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0), in combineSHL()
14456 Op.getValueType() != MVT::i64) in combineADDToADDZE()
14461 Cmp.getOperand(0).getValueType() != MVT::i64) in combineADDToADDZE()
14484 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Glue); in combineADDToADDZE()
14501 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z, in combineADDToADDZE()
14502 DAG.getConstant(NegConstant, DL, MVT::i64)); in combineADDToADDZE()
14504 SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue), in combineADDToADDZE()
14505 AddOrZ, DAG.getConstant(-1ULL, DL, MVT::i64)); in combineADDToADDZE()
14506 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
14516 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z, in combineADDToADDZE()
14517 DAG.getConstant(NegConstant, DL, MVT::i64)); in combineADDToADDZE()
14519 SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue), in combineADDToADDZE()
14520 DAG.getConstant(0, DL, MVT::i64), AddOrZ); in combineADDToADDZE()
14521 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
14558 if (Op0.getValueType() != MVT::i128 || N->getValueType(0) != MVT::i64) in combineTRUNCATE()
14578 Op0.getValueType() == MVT::i128 && in combineTRUNCATE()
14579 Op0.getOperand(0).getValueType() == MVT::f128) { in combineTRUNCATE()
14580 SDValue Bitcast = DCI.DAG.getBitcast(MVT::v2i64, Op0.getOperand(0)); in combineTRUNCATE()
14582 ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Bitcast, in combineTRUNCATE()
14583 DCI.DAG.getTargetConstant(EltToExtract, dl, MVT::i32)); in combineTRUNCATE()
14626 if (Subtarget.hasP9Vector() && VT == MVT::f128) in hasBitPreservingFPLogic()
14628 return VT == MVT::f32 || VT == MVT::f64 || in hasBitPreservingFPLogic()
14629 VT == MVT::v4f32 || VT == MVT::v2f64; in hasBitPreservingFPLogic()
14659 if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8) in combineABS()
14676 DAG.getTargetConstant(0, dl, MVT::i32)); in combineABS()
14680 if (N->getOperand(0).getValueType() == MVT::v4i32 && in combineABS()
14685 DAG.getTargetConstant(1, dl, MVT::i32)); in combineABS()
14715 if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8) in combineVSelect()
14749 DAG.getTargetConstant(0, dl, MVT::i32)); in combineVSelect()