Lines Matching refs:IsZExt
159 const TargetRegisterClass *RC, bool IsZExt = true,
166 unsigned DestReg, bool IsZExt);
467 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
496 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
500 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
833 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
858 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); in PPCEmitCmp()
859 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
931 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
933 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
937 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; in PPCEmitCmp()
939 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; in PPCEmitCmp()
945 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
951 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
1813 unsigned DestReg, bool IsZExt) { in PPCEmitIntExt() argument
1820 if (!IsZExt) { in PPCEmitIntExt()
1915 bool IsZExt = isa<ZExtInst>(I); in SelectIntExt() local
1941 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt)) in SelectIntExt()
2308 bool IsZExt = false; in tryToFoldLoadIntoMI() local
2315 IsZExt = true; in tryToFoldLoadIntoMI()
2326 IsZExt = true; in tryToFoldLoadIntoMI()
2364 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt, in tryToFoldLoadIntoMI()