207       MachineOperand &TrueValue = (*I)->getOperand(1);  in expandAndMergeISELs()  local
213       if (useSameRegister(Dest, TrueValue) &&  in expandAndMergeISELs()
223       } else if (useSameRegister(TrueValue, FalseValue)) {  in expandAndMergeISELs()
237             .add(TrueValue)  in expandAndMergeISELs()
274     MachineOperand &TrueValue = (*MI)->getOperand(1);  in handleSpecialCases()  local
283     bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);  in handleSpecialCases()
306     if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {  in handleSpecialCases()
314           .add(TrueValue)  in handleSpecialCases()
441     MachineOperand &TrueValue = MI->getOperand(1);  // Value to store if  in populateBlocks()  local
448     LLVM_DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n");  in populateBlocks()
454     bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);  in populateBlocks()
462           .add(TrueValue)  in populateBlocks()
466       TrueBlock->addLiveIn(TrueValue.getReg());  in populateBlocks()
477       NewSuccessor->addLiveIn(TrueValue.getReg());  in populateBlocks()