208       MachineOperand &FalseValue = (*I)->getOperand(2);  in expandAndMergeISELs()  local
214           useSameRegister(Dest, FalseValue)) {  in expandAndMergeISELs()
223       } else if (useSameRegister(TrueValue, FalseValue)) {  in expandAndMergeISELs()
238             .add(FalseValue);  in expandAndMergeISELs()
275     MachineOperand &FalseValue = (*MI)->getOperand(2);  in handleSpecialCases()  local
284     bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);  in handleSpecialCases()
306     if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {  in handleSpecialCases()
315           .add(FalseValue);  in handleSpecialCases()
443     MachineOperand &FalseValue = MI->getOperand(2); // Value to store if  in populateBlocks()  local
449     LLVM_DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n");  in populateBlocks()
455     bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);  in populateBlocks()
471       FalseBlock->addLiveIn(FalseValue.getReg());  in populateBlocks()
478       NewSuccessor->addLiveIn(FalseValue.getReg());  in populateBlocks()
487           .add(FalseValue)  in populateBlocks()